Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

E-8 Vol. 3
INTERPRETING MACHINE-CHECK ERROR CODES
The ROB time-out counter is prescaled by the
8-bit PIC timer which is a divide by 128 of the
bus clock the bus clock is 1:2, 1:3, 1:4 of the
core clock). When a carry out of the 8-bit PIC
timer occurs, the ROB counter counts up by
one. While this bit is asserted, it cannot be
overwritten by another error.
39-41 Reserved Reserved
42 Hard error This bit is asserted in IA32_MCi_STATUS if this
component has initiated a bus transactions
which has received a hard error response. While
this bit is asserted, it cannot be overwritten.
43 IERR This bit is asserted in IA32_MCi_STATUS if this
component has experienced a failure that
causes the IERR pin to be asserted. While this
bit is asserted, it cannot be overwritten.
44 Reserved Reserved
45 Reserved Reserved
46 Reserved Reserved
47-54 Reserved Reserved
55-56 Reserved Reserved.
Status register
validity
indicators
1
57-63
NOTES:
1. These fields are architecturally defined. Refer to Chapter 14, “Machine-Check Architecture,”
for more information.
Table E-4. Incremental Bus Error Codes of Machine Check for Processors Based on
Intel Core Microarchitecture
Type Bit No. Bit Function Bit Description