Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 18-81
DEBUGGING AND PERFORMANCE MONITORING
18.17.2 Performance Monitoring Facility in the Uncore
The “uncore” in Intel microarchitecture (Nehalem) refers to subsystems in the phys-
ical processor package that are shared by multiple processor cores. Some of the sub-
systems in the uncore include the L3 cache, Intel QuickPath Interconnect link logic,
and integrated memory controller. The performance monitoring facilities inside the
uncore operates in the same clock domain as the uncore (U-clock domain), which is
usually different from the processor core clock domain.
The performance monitoring facilities available in the U-clock domain consist of:
• Eight General-purpose counters (MSR_UNCORE_PerfCntr0 through
MSR_UNCORE_PerfCntr0). The counters are 48 bits wide. Each counter is
associated with a configuration MSR, MSR_UNCORE_PerfEvtSelx, to specify
event code, event mask and other event qualification fields. A set of global
uncore performance counter enabling/overflow/status control MSRs are also
provided for software.
• Performance monitoring in the uncore provides an address/opcode match MSR
that provides event qualification control based on address value or QPI command
opcode.
• One fixed-function counter, MSR_UNCORE_FixedCntr0. The fixed-function
uncore counter increments at the rate of the U-clock when enabled.
The frequency of the uncore clock domain can be determined from the uncore
clock ratio which is available in the PCI configuration space register at offset C0H
under device number 0 and Function 0.
18.17.2.1 Uncore Performance Monitoring Management Facility
MSR_UNCORE_PERF_GLOBAL_CTRL provides bit fields to enable/disable general-
purpose and fixed-function counters in the uncore. Figure 18-29 shows the layout of
MSR_UNCORE_PERF_GLOBAL_CTRL for an uncore that is shared by four processor
cores in a physical package.
• EN_PCn (bit n, n = 0, 7): When set, enables counting for the general-purpose
uncore counter MSR_UNCORE_PerfCntr n.
• EN_FC0 (bit 32): When set, enables counting for the fixed-function uncore
counter MSR_UNCORE_FixedCntr0.
• EN_PMI_COREn (bit n, n = 0, 3 if four cores are present): When set, processor
core n is programmed to receive an interrupt signal from any interrupt enabled
uncore counter. PMI delivery due to an uncore counter overflow is enabled by
setting IA32_DEBUG_CTL.Offcore_PMI_EN to 1.
• PMI_FRZ (bit 63): When set, all U-clock uncore counters are disabled when any
one of them signals a performance interrupt. Software must explicitly re-enable
the counter by setting the enable bits in MSR_UNCORE_PERF_GLOBAL_CTRL
upon exit from the ISR.