Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

F-4 Vol. 3
APIC BUS MESSAGE FORMATS
Cycles 21 through 28 are used to arbitrate for the lowest priority processor. The
processors participating in the arbitration drive their inverted processor priority on
the bus. Only the local APICs having free interrupt slots participate in the lowest
priority arbitration. If no such APIC exists, the message will be rejected, requiring it
to be tried at a later time.
Cycles 29 through 32 are also used for arbitration in case two or more processors
have the same lowest priority. In the lowest priority delivery mode, all combinations
of errors in cycle 33 (A2 A2) will set the “accept error” bit in the error status register
(see Figure 9-13). Arbitration priority update is performed in cycle 20, and is not
affected by errors detected in cycle 33. Only the local APIC that wins in the lowest
13 D7 D6 D7-D0 = Destination
14 D5 D4
15 D3 D2
16 D1 D0
17 C C Checksum for cycles 6-16
18 0 0
19 A A Status cycle 0
20 A1 A1 Status cycle 1
21 P7 0 P7 - P0 = Inverted Processor Priority
22 P6 0
23 P5 0
24 P4 0
25 P3 0
26 P2 0
27 P1 0
28 P0 0
29 ArbID3 0 Arbitration ID 3 -0
30 ArbID2 0
31 ArbID1 0
32 ArbID0 0
33 A2 A2 Status Cycle
34 0 0 Idle
Table F-3. Non-Focused Lowest Priority Message (34 Cycles) (Contd.)
Cycle Bit0 Bit1