Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

G-2 Vol. 3
VMX CAPABILITY REPORTING FACILITY
The first processors to support VMX operation use the write-back type. The
values used are given in Table G-1.
If software needs to access these data structures (e.g., to modify the contents of
the MSR bitmaps), it can configure the paging structures to map them into the
linear-address space. If it does so, it should establish mappings that use the
memory type reported in this MSR.
1
• If bit 54 is read as 1, the logical processor reports information in the VM-exit
instruction-information field on VM exits due to execution of the INS and OUTS
instructions. This reporting is done only if this bit is read as 1.
• Bit 55 is read as 1 if any VMX controls that default to 1 may be cleared to 0. See
Appendix G.2 for details. It also reports support for the VMX capability MSRs
IA32_VMX_TRUE_PINBASED_CTLS, IA32_VMX_TRUE_PROCBASED_CTLS,
IA32_VMX_TRUE_EXIT_CTLS, and IA32_VMX_TRUE_ENTRY_CTLS. See
Appendix G.3.1, Appendix G.3.2, Appendix G.4, and Appendix G.5 for details.
• The values of bits 47:45 and bits 63:56 are reserved and are read as 0.
G.2 RESERVED CONTROLS AND DEFAULT SETTINGS
As noted in Chapter 20, “Virtual-Machine Control Structures”, certain VMX controls
are reserved and must be set to a specific value (0 or 1) determined by the processor.
The specific value to which a reserved control must be set is its default setting.
2. If the MTRRs are disabled by clearing the E bit (bit 11) in the IA32_MTRR_DEF_TYPE MSR, the
logical processor uses the UC memory type to access the indicated data structures, regardless of
the value reported in bits 53:50 in the IA32_VMX_BASIC MSR. The processor will also use the UC
memory type if the setting of CR0.CD on this logical processor (or another logical processor on
the same physical processor) would cause it to do so for all memory accesses. Note that the val-
ues of IA32_MTRR_DEF_TYPE.E and CR0.CD do not affect the value reported in
IA32_VMX_BASIC[53:50].
Table G-1. Memory Types Used For VMCS Access
Value(s) Field
0 Uncacheable (UC)
1–5 Not used
6 Write Back (WB)
7–15 Not used
1. Alternatively, software may map any of these regions or structures with the UC memory type.
(This may be necessary for the MSEG header.) Doing so is discouraged unless necessary as it will
cause the performance of software accesses to those structures to suffer. Note that the proces-
sor will continue to use the memory type reported in the VMX capability MSR IA32_VMX_BASIC
with the exceptions noted.