Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3 G-3
VMX CAPABILITY REPORTING FACILITY
Software can discover the default setting of a reserved control by consulting the
appropriate VMX capability MSR (see Appendix G.3 through Appendix G.5).
Future processors may define new functionality for one or more reserved controls.
Such processors would allow each newly defined control to be set either to 0 or to 1.
Software that does not desire a control’s new functionality should set the control to
its default setting. For that reason, it is useful for software to know the default
settings of the reserved controls.
Default settings partition the various controls into the following classes:
• Always-flexible. These have never been reserved.
• Default0. These are (or have been) reserved with a default setting of 0.
• Default1. They are (or have been) reserved with a default setting of 1.
As noted in Appendix G.1, a logical processor uses bit 55 of the
IA32_VMX_BASIC MSR to indicate whether any of the default1 controls may be 0:
• If bit 55 of the IA32_VMX_BASIC MSR is read as 0, all the default1 controls are
reserved and must be 1. VM entry will fail if any of these controls are 1 (see
Section 22.2.1).
• If bit 55 of the IA32_VMX_BASIC MSR is read as 1, not all the default1 controls
are reserved, and some (but not necessarily all) may be 0. The CPU supports four
(4) new VMX capability MSRs: IA32_VMX_TRUE_PINBASED_CTLS,
IA32_VMX_TRUE_PROCBASED_CTLS, IA32_VMX_TRUE_EXIT_CTLS, and
IA32_VMX_TRUE_ENTRY_CTLS. See Appendix G.3 through Appendix G.5 for
details. (These MSRs are not supported if bit 55 of the IA32_VMX_BASIC MSR is
read as 0.)
See Section 26.5.1 for recommended software algorithms for proper capability
detection of the default1 controls.
G.3 VM-EXECUTION CONTROLS
There are separate capability MSRs for the pin-based VM-execution controls, the
primary processor-based VM-execution controls, and the secondary processor-based
VM-execution controls. These are described in Appendix G.3.1, Appendix G.3.2, and
Appendix G.3.3, respectively.
G.3.1 Pin-Based VM-Execution Controls
The IA32_VMX_PINBASED_CTLS MSR (index 481H) reports on the allowed settings
of most of the pin-based VM-execution controls (see Section 20.6.1):
• Bits 31:0 indicate the allowed 0-settings of these controls. VM entry fails if
bit X is 0 in the pin-based VM-execution controls and bit X is 1 in this MSR.
Exceptions are made for the pin-based VM-execution controls in the default1
class (see Appendix G.2). These are bits 1, 2, and 4; the corresponding bits of