Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

G-4 Vol. 3
VMX CAPABILITY REPORTING FACILITY
the IA32_VMX_PINBASED_CTLS MSR are always read as 1. The treatment of
these controls by VM entry is determined by bit 55 in the IA32_VMX_BASIC MSR:
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any pin-
based VM-execution control in the default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the
IA32_VMX_TRUE_PINBASED_CTLS MSR (see below) reports which of the
pin-based VM-execution controls in the default1 class can be 0 on VM entry.
• Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if
bit X is 1 in the pin-based VM-execution controls and bit 32+X is 0 in this MSR.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1,
the IA32_VMX_TRUE_PINBASED_CTLS MSR (index 48DH) reports on the allowed
settings of all of the pin-based VM-execution controls:
• Bits 31:0 indicate the allowed 0-settings of these controls. VM entry fails if bit X
is 0 in the pin-based VM-execution controls and bit X is 1 in this MSR. There are
no exceptions.
• Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if bit X
is 1 in the pin-based VM-execution controls and bit 32+X is 0 in this MSR.
Note that it is necessary for software to consult only one of the capability MSRs to
determine the allowed settings of the pin-based VM-execution controls:
• If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the
allowed settings of the pin-based VM-execution controls is contained in
the IA32_VMX_PINBASED_CTLS MSR. (The IA32_VMX_TRUE_PINBASED_CTLS
MSR is not supported.)
• If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the
allowed settings of the pin-based VM-execution controls is contained in
the IA32_VMX_TRUE_PINBASED_CTLS MSR. Assuming that software knows that
the default1 class of pin-based VM-execution controls contains bits 1, 2, and 4,
there is no need for software to consult the IA32_VMX_PINBASED_CTLS MSR.
G.3.2 Primary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS MSR (index 482H) reports on the allowed
settings of most of the primary processor-based VM-execution controls (see Section
20.6.2):
• Bits 31:0 indicate the allowed 0-settings of these controls. VM entry fails if bit X
is 0 in the primary processor-based VM-execution controls and bit X is 1 in this
MSR.
Exceptions are made for the primary processor-based VM-execution controls in
the default1 class (see Appendix G.2). These are bits 1, 4–6, 8, 13–16, and 26;
the corresponding bits of the IA32_VMX_PROCBASED_CTLS MSR are always read
as 1. The treatment of these controls by VM entry is determined by bit 55 in the
IA32_VMX_BASIC MSR: