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Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

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Table Of Contents
Vol. 3 G-5
VMX CAPABILITY REPORTING FACILITY
— If bit 55 in the IA32_VMX_BASIC MSR is read as 0, VM entry fails if any of the
primary processor-based VM-execution controls in the default1 class is 0.
— If bit 55 in the IA32_VMX_BASIC MSR is read as 1, the
IA32_VMX_TRUE_PROCBASED_CTLS MSR (see below) reports which of the
primary processor-based VM-execution controls in the default1 class can be 0
on VM entry.
• Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if bit X
is 1 in the primary processor-based VM-execution controls and bit 32+X is 0 in
this MSR.
If bit 55 in the IA32_VMX_BASIC MSR is read as 1,
the IA32_VMX_TRUE_PROCBASED_CTLS MSR (index 48EH) reports on the allowed
settings of all of the primary processor-based VM-execution controls:
• Bits 31:0 indicate the allowed 0-settings of these controls. VM entry fails if bit X
is 0 in the primary processor-based VM-execution controls and bit X is 1 in this
MSR. There are no exceptions.
• Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if bit X
is 1 in the primary processor-based VM-execution controls and bit 32+X is 0 in
this MSR.
Note that it is necessary for software to consult only one of the capability MSRs to
determine the allowed settings of the primary processor-based VM-execution
controls:
• If bit 55 in the IA32_VMX_BASIC MSR is read as 0, all information about the
allowed settings of the primary processor-based VM-execution controls is
contained in the IA32_VMX_PROCBASED_CTLS MSR. (The
IA32_VMX_TRUE_PROCBASED_CTLS MSR is not supported.)
• If bit 55 in the IA32_VMX_BASIC MSR is read as 1, all information about the
allowed settings of the pin-based VM-execution controls is contained in the
IA32_VMX_TRUE_PROCBASED_CTLS MSR. Assuming that software knows that
the default1 class of pin-based VM-execution controls contains bits 1, 4–6, 8,
13–16, and 26, there is no need for software to consult the
IA32_VMX_PROCBASED_CTLS MSR.
G.3.3 Secondary Processor-Based VM-Execution Controls
The IA32_VMX_PROCBASED_CTLS2 MSR (index 48BH) reports on the allowed
settings of the secondary processor-based VM-execution controls (see Section
20.6.2). VM entries perform the following checks:
• Bits 31:0 indicate the allowed 0-settings of these controls. These bits are always
0. This fact indicates that VM entry does not fail simply because if the “activate
secondary controls” primary processor-based VM-execution control is 1 and
some bit is 0 in the secondary processor-based VM-execution controls.
• Bits 63:32 indicate the allowed 1-settings of these controls. VM entry fails if the
“activate secondary controls” primary processor-based VM-execution control is