Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

G-8 Vol. 3
VMX CAPABILITY REPORTING FACILITY
VMX-preemption timer (if it is active) counts down by 1 every time bit X in the
TSC changes due to a TSC increment.
• Bits 8:6 report, as a bitmap, the activity states supported by the implemen-
tation:
— Bit 6 reports (if set) the support for activity state 1 (HLT).
— Bit 7 reports (if set) the support for activity state 2 (shutdown).
— Bit 8 reports (if set) the support for activity state 3 (wait-for-SIPI).
If an activity state is not supported, the implementation causes a VM entry to fail
if it attempts to establish that activity state. Note that all implementations
support VM entry to activity state 0 (active).
• Bits 24:16 indicate the number of CR3-target values supported by the processor.
This number is a value between 0 and 256, inclusive (bit 24 is set if and only if
bits 23:16 are clear).
• Bits 27:25 is used to compute the recommended maximum number of MSRs that
should appear in the VM-exit MSR-store list, the VM-exit MSR-load list, or the
VM-entry MSR-load list. Specifically, if the value bits 27:25 of IA32_VMX_MISC is
N, then 512 * (N + 1) is the recommended maximum number of MSRs to be
included in each list. If the limit is exceeded, undefined processor behavior may
result (including a machine check during the VMX transition).
• Bits 63:32 report the 32-bit MSEG revision identifier used by the processor.
• Bit 5, bits 15:9, and bits 31:28 are reserved and are read as 0.
G.7 VMX-FIXED BITS IN CR0
The IA32_VMX_CR0_FIXED0 MSR (index 486H) and IA32_VMX_CR0_FIXED1 MSR
(index 487H) indicate how bits in CR0 may be set in VMX operation. They report on
bits in CR0 that are allowed to be 0 and to be 1, respectively, in VMX operation. If
bit X is 1 in IA32_VMX_CR0_FIXED0, then that bit of CR0 is fixed to 1 in VMX opera-
tion. Similarly, if bit X is 0 in IA32_VMX_CR0_FIXED1, then that bit of CR0 is fixed to
0 in VMX operation. It is always the case that, if bit X is 1 in IA32_VMX_CR0_FIXED0,
then that bit is also 1 in IA32_VMX_CR0_FIXED1; if bit X is 0 in
IA32_VMX_CR0_FIXED1, then that bit is also 0 in IA32_VMX_CR0_FIXED0. Thus,
each bit in CR0 is either fixed to 0 (with value 0 in both MSRs), fixed to 1 (1 in both
MSRs), or flexible (0 in IA32_VMX_CR0_FIXED0 and 1 in IA32_VMX_CR0_FIXED1).
G.8 VMX-FIXED BITS IN CR4
The IA32_VMX_CR4_FIXED0 MSR (index 488H) and IA32_VMX_CR4_FIXED1 MSR
(index 489H) indicate how bits in CR4 may be set in VMX operation. They report on
bits in CR4 that are allowed to be 0 and 1, respectively, in VMX operation. If bit X is 1
in IA32_VMX_CR4_FIXED0, then that bit of CR4 is fixed to 1 in VMX operation. Simi-