Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-84 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
• CLR_OVF_PCn (bit n, n = 0, 7): Set this bit to clear the overflow status for
general-purpose uncore counter MSR_UNCORE_PerfCntr n. Writing a value other
than 1 is ignored.
• CLR_OVF_FC0 (bit 32): Set this bit to clear the overflow status for the fixed-
function uncore counter MSR_UNCORE_FixedCntr0. Writing a value other than 1
is ignored.
• CLR_OVF_PMI (bit 61): Set this bit to clear the OVF_PMI flag in
MSR_UNCORE_PERF_GLOBAL_STATUS. Writing a value other than 1 is ignored.
• CLR_CHG (bit 63): Set this bit to clear the CHG flag in
MSR_UNCORE_PERF_GLOBAL_STATUS register. Writing a value other than 1 is
ignored.
18.17.2.2 Uncore Performance Event Configuration Facility
MSR_UNCORE_PerfEvtSel0 through MSR_UNCORE_PerfEvtSel7 are used to select
performance event and configure the counting behavior of the respective uncore
performance counter. Each uncore PerfEvtSel MSR is paired with an uncore perfor-
mance counter. Each uncore counter must be locally configured using the corre-
sponding MSR_UNCORE_PerfEvtSelx and counting must be enabled using the
respective EN_PCx bit in MSR_UNCORE_PERF_GLOBAL_CTRL. Figure 18-32 shows
the layout of MSR_UNCORE_PERFEVTSELx.
• Event Select (bits 7:0): Selects the event logic unit used to detect uncore events.
• Unit Mask (bits 15:8) : Condition qualifiers for the event selection logic specified
in the Event Select field.
• OCC_CTR_RST (bit17): When set causes the queue occupancy counter
associated with this event to be cleared (zeroed). Writing a zero to this bit will be
ignored. It will always read as a zero.
Figure 18-32. Layout of MSR_UNCORE_PERFEVTSELx MSRs
31
INV—Invert counter mask
EN—Enable counters
E—Edge detect
OCC_CTR_RST—Rest Queue Occ
87
0
Event Select
Counter Mask
19 1618 15172021222324
Reserved
Unit Mask (UMASK)
(CMASK)
63
PMI—Enable PMI on overflow
RESET Value — 0x00000000_00000000