Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3B Index -3
INDEX
description of, 8-1
performing, 8-2
Bus
errors detected with MCA, 14-28
hold, 17-42
locking, 7-3, 17-42
Byte order, 1-6
C
C (conforming) flag, segment descriptor, 4-16
C1 flag, x87 FPU status word, 17-10, 17-20
C2 flag, x87 FPU status word, 17-11
Cache control, 10-30
adaptive mode, L1 Data Cache, 10-26
cache management instructions, 10-25, 10-26
cache mechanisms in IA-32 processors, 17-34
caching terminology, 10-7
CD flag, CR0 control register, 10-15, 17-26
choosing a memory type, 10-12
CPUID feature flag, 10-26
flags and fields, 10-14
flushing TLBs, 10-28
G (global) flag
page-directory entries, 10-19, 10-29
page-table entries, 10-19, 10-29
internal caches, 10-1
MemTypeGet() function, 10-41
MemTypeSet() function, 10-42
MESI protocol, 10-7, 10-13
methods of caching available, 10-8
MTRR initialization, 10-40
MTRR precedences, 10-39
MTRRs, description of, 10-30
multiple-processor considerations, 10-44
NW flag, CR0 control register, 10-18, 17-26
operating modes, 10-17
overview of, 10-1
page attribute table (PAT), 10-46
PCD flag
CR3 control register, 10-19
page-directory entries, 10-19, 10-20, 10-46
page-table entries, 10-19, 10-20, 10-46
PGE (page global enable) flag, CR4 control register
, 10-19
precedence of controls, 10-20
preventing caching, 10-24
protocol, 10-13
PWT flag
CR3 control register, 10-19
page-directory entries, 10-19, 10-46
page-table entries, 10-19, 10-46
remapping memory types, 10-40
setting up memory ranges with MTRRs, 10-32
shared mode, L1 Data Cache, 10-26
variable-range MTRRs, 10-34
Caches, 2-10
cache hit, 10-7
cache line, 10-7
cache line fill, 10-7
cache write hit, 10-7
description of, 10-1
effects of a locked operation on internal processor
caches
, 7-7
enabling, 8-8
management, instructions, 2-31, 10-25
Caching
cache control protocol, 10-13
cache line, 10-7
cache management instructions, 10-25
cache mechanisms in IA-32 processors, 17-34
caching terminology, 10-7
choosing a memory type, 10-12
flushing TLBs, 10-28
implicit caching, 10-27
internal caches, 10-1
L1 (level 1) cache, 10-5
L2 (level 2) cache, 10-5
L3 (level 3) cache, 10-5
methods of caching available, 10-8
MTRRs, description of, 10-30
operating modes, 10-17
overview of, 10-1
self-modifying code, effect on, 10-27, 17-35
snooping, 10-8
store buffer, 10-29
TLBs, 10-6
UC (strong uncacheable) memory type, 10-8
UC- (uncacheable) memory type, 10-9
WB (write back) memory type, 10-10
WC (write combining) memory type, 10-9
WP (write protected) memory type, 10-10
write-back caching, 10-8
WT (write through) memory type, 10-9
Call gates
16-bit, interlevel return from, 17-38
accessing a code segment through, 4-22
description of, 4-19
for 16-bit and 32-bit code modules, 16-2
IA-32e mode, 4-20
introduction to, 2-5
mechanism, 4-22
privilege level checking rules, 4-23
CALL instruction, 2-6, 3-11, 4-14, 4-15, 4-22, 4-29,
6-3, 6-12, 6-13, 16-7
Caller access privileges, checking, 4-37
Calls
16 and 32-bit code segments, 16-4
controlling operand-size attribute, 16-7
returning from, 4-28
Capability MSRs
See VMX capability MSRs
Catastrophic shutdown detector
Thermal monitoring
catastrophic shutdown detector, 13-10
catastrophic shutdown detector, 13-9