Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

INDEX
Index-8 Vol. 3B
G0-G3 (global breakpoint enable) flags
DR7 register, 18-5
Gate descriptors
call gates, 4-19
description of, 4-18
IA-32e mode, 4-20
Gates, 2-5
IA-32e mode, 2-6
GD (general detect enable) flag
DR7 register, 18-5, 18-12
GDT
description of, 2-5, 3-21
IA-32e mode, 2-5
index field of segment selector, 3-9
initializing, 8-12
paging of, 2-8
pointers to exception/interrupt handlers, 5-16
segment descriptors in, 3-13
selecting with TI flag of segment selector, 3-10
task switching, 6-12
task-gate descriptor, 6-11
TSS descriptors, 6-7
use in address translation, 3-8
GDTR register
description of, 2-5, 2-9, 2-16, 3-21
IA-32e mode, 2-5, 2-16
limit, 4-7
loading during initialization, 8-12
storing, 3-21
GE (global exact breakpoint enable) flag
DR7 register, 18-5, 18-12
General-detect exception condition, 18-12
General-protection exception (#GP), 3-17, 4-9, 4-10,
4-16, 4-17, 5-13, 5-19, 5-50, 6-7, 17-16,
17-28, 17-29, 17-40, 17-42, 18-2
General-purpose registers, saved in TSS, 6-5
Global control MSRs, 14-3
Global descriptor table register (see GDTR)
Global descriptor table (see GDT)
H
HALT state
relationship to SMI interrupt, 25-5, 25-18
Hardware reset
description of, 8-1
processor state after reset, 8-2
state of MTRRs following, 10-30
value of SMBASE following, 25-5
Hexadecimal numbers, 1-8
high-temperature interrupt enable bit, 13-20
HITM# line, 10-8
HLT instruction, 2-31, 4-34, 5-39, 21-3, 25-18, 25-19
Hyper-Threading Technology
architectural state of a logical processor, 7-47
architecture description, 7-39
caches, 7-44
counting clockticks, 18-126
debug registers, 7-42
description of, 7-35, 17-5
detecting, 7-51, 7-56, 7-57, 7-58
executing multiple threads, 7-38
execution-based timing loops, 7-73
external signal compatibility, 7-46
halting logical processors, 7-71
handling interrupts, 7-38
HLT instruction, 7-65
IA32_MISC_ENABLE MSR, 7-43, 7-48
initializing IA-32 processors with, 7-37
introduction of into the IA-32 architecture, 17-5
local a, 7-40
local APIC
functionality in logical processor, 7-41
logical processors, identifying, 7-52
machine check architecture, 7-42
managing idle and blocked conditions, 7-64
mapping resources, 7-49
memory ordering, 7-43
microcode update resources, 7-44, 7-48, 8-46
MP systems, 7-39
MTRRs, 7-41, 7-47
multi-threading feature flag, 7-36
multi-threading support, 7-35
PAT, 7-42
PAUSE instruction, 7-65, 7-66
performance monitoring, 18-118, 18-129
performance monitoring counters, 7-43, 7-47
placement of locks and semaphores, 7-73
required operating system support, 7-68
scheduling multiple threads, 7-72
self modifying code, 7-44
serializing instructions, 7-43
spin-wait loops
PAUSE instructions in, 7-69, 7-71
thermal monitor, 7-45
TLBs, 7-45
I
IA32, 14-5
IA-32 Intel architecture
compatibility, 17-1
processors, 17-1
IA32e mode
registers and mode changes, 8-16
IA-32e mode
address translation (2-MByte pages), 3-44
address translation (4-KByte pages), 3-43
call gates, 4-20
code segment descriptor, 4-5
D flag, 4-5
data structures and initialization, 8-15
debug registers, 2-9
debug store area, 18-101
descriptors, 2-6
DPL field, 4-5