Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

INDEX
Index-12 Vol. 3B
handling through a task gate in virtual-8086 mode
, 15-21
handling through a trap or interrupt gate in
virtual-8086 mode, 15-18
IA-32e mode, 2-7, 2-17
IDT, 5-12
IDTR, 2-17
initializing for protected-mode operation, 8-13
interrupt descriptor table register (see IDTR)
interrupt descriptor table (see IDT)
list of, 5-3, 15-8
local APIC, 9-1
maskable hardware interrupts, 2-13
masking maskable hardware interrupts, 5-9
masking when switching stack segments, 5-11
message signalled interrupts, 9-65
on-die sensors for, 13-10
overview of, 5-1
priorities among simultaneous exceptions and
interrupts, 5-11
priority, 9-57
propagation delay, 17-30
real-address mode, 15-8
restarting a task or program, 5-7
software, 5-67
sources of, 9-1
summary of, 5-3
thermal monitoring, 13-10
user defined, 5-2, 5-67
valid APIC interrupts, 9-33
vectors, 5-2
virtual-8086 mode, 15-8
INTO instruction, 2-7, 3-11, 5-6, 5-32, 18-13
INTR# pin, 5-2, 5-9
Invalid opcode exception (#UD), 2-22, 5-34, 5-64,
11-1, 17-7, 17-15, 17-27, 17-28, 17-29,
18-4, 25-4
Invalid TSS exception (#TS), 5-42, 6-8
Invalid-operation exception, x87 FPU, 17-15, 17-19
INVD instruction, 2-31, 4-34, 10-25, 17-6
INVLPG instruction, 2-31, 4-34, 17-6, 27-5, 27-6
IOPL (I/O privilege level) field, EFLAGS register
description of, 2-13
on return from exception, interrupt handler, 5-18
sensitive instructions in virtual-8086 mode,
15-15
virtual interrupt, 2-14, 2-15
IPI (see interprocessor interrupt)
IRET instruction, 3-11, 5-9, 5-10, 5-18, 5-19, 5-25,
6-13, 7-25, 15-6, 15-29, 21-15
IRETD instruction, 2-14, 7-25
IRR
Interrupt Request Register, 9-20, 9-25, 9-53
IRR (interrupt request register), local APIC, 9-60
ISR
In Service Register, 9-19, 9-25, 9-53
I/O
breakpoint exception conditions, 18-12
in virtual-8086 mode, 15-15
instruction restart flag
SMM revision identifier field, 25-20
instruction restart flag, SMM revision identifier
field, 25-21
IO_SMI bit, 25-15
I/O permission bit map, TSS, 6-6
map base address field, TSS, 6-6
restarting following SMI interrupt, 25-20
saving I/O state, 25-15
SMM state save map, 25-15
I/O APIC, 9-54
bus arbitration, 9-53
description of, 9-1
external interrupts, 5-4
information about, 9-1
interrupt sources, 9-2
local APIC and I/O APIC, 9-3, 9-4
overview of, 9-1
valid interrupts, 9-33
See also: local APIC
J
JMP instruction, 2-6, 3-11, 4-14, 4-15, 4-22, 6-3,
6-12, 6-13
K
KEN# pin, 10-19, 17-43
L
L0-L3 (local breakpoint enable) flags
DR7 register, 18-5
L1 (level 1) cache
caching methods, 10-8
CPUID feature flag, 10-26
description of, 10-5
effect of using write-through memory, 10-12
introduction of, 17-34
invalidating and flushing, 10-25
MESI cache protocol, 10-13
shared and adaptive mode, 10-26
L2 (level 2) cache
caching methods, 10-8
description of, 10-5
disabling, 10-25
effect of using write-through memory, 10-12
introduction of, 17-34
invalidating and flushing, 10-25
MESI cache protocol, 10-13
L3 (level 3) cache
caching methods, 10-8
description of, 10-5
disabling and enabling, 10-19, 10-25
effect of using write-through memory, 10-12
introduction of, 17-35
invalidating and flushing, 10-25