Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3B Index -15
INDEX
WB (write back), 10-10
WC (write combining), 10-9
WP (write protected), 10-10
writing values across pages with different
memory types, 10-23
WT (write through), 10-9
MemTypeGet() function, 10-41
MemTypeSet() function, 10-42
MESI cache protocol, 10-7, 10-13
Message address register, 9-66
Message data register format, 9-67
Message signalled interrupts
message address register, 9-65
message data register format, 9-65
MFENCE instruction, 2-21, 7-9, 7-22, 7-23, 7-25
Microcode update facilities
authenticating an update, 8-48
BIOS responsibilities, 8-49
calling program responsibilities, 8-52
checksum, 8-44
extended signature table, 8-41
family 0FH processors, 8-37
field definitions, 8-37
format of update, 8-37
function 00H presence test, 8-56
function 01H write microcode update data, 8-57
function 02H microcode update control, 8-62
function 03H read microcode update data, 8-63
general description, 8-37
HT Technology, 8-46
INT 15H-based interface, 8-55
overview, 8-36
process description, 8-37
processor identification, 8-41
processor signature, 8-41
return codes, 8-64
update loader, 8-45
update signature and verification, 8-47
update specifications, 8-49
VMX non-root operation, 21-19, 27-12
VMX support
early loading, 27-12
late loading, 27-12
virtualization issues, 27-11
Mixing 16-bit and 32-bit code
in IA-32 processors, 17-38
overview, 16-1
MMX technology
debugging MMX code, 11-6
effect of MMX instructions on pending x87
floating-point exceptions, 11-6
emulation of the MMX instruction set, 11-1
exceptions that can occur when executing MMX
instructions, 11-1
introduction of into the IA-32 architecture
, 17-3
register aliasing, 11-1
state, 11-1
state, saving and restoring, 11-4
system programming, 11-1
task or context switches, 11-5
using TS flag to control saving of MMX state,
12-10
Mode switching
example, 8-19
real-address and protected mode, 8-17
to SMM, 25-3
Model and stepping information, following processor
initialization or reset, 8-5
Model-specific registers (see MSRs)
Modes of operation (see Operating modes)
MONITOR instruction, 21-4
MOV instruction, 3-11, 4-11
MOV (control registers) instructions, 2-29, 2-30,
4-34, 7-25, 8-17
MOV (debug registers) instructions, 2-31, 4-34, 7-25,
18-12
MOVNTDQ instruction, 7-9, 10-7, 10-26
MOVNTI instruction, 2-21, 7-9, 10-7, 10-26
MOVNTPD instruction, 7-9, 10-7, 10-26
MOVNTPS instruction, 7-9, 10-7, 10-26
MOVNTQ instruction, 7-9, 10-7, 10-26
MP (monitor coprocessor) flag
CR0 control register, 2-21, 2-22, 5-36, 8-6, 8-8,
11-1, 17-10
MSR, B-126
Model Specific Register, 9-16, 9-17, 9-18
MSRs
architectural, B-2
description of, 8-9
introduction of in IA-32 processors, 17-42
introduction to, 2-9
list of, B-1
machine-check architecture, 14-3
P6 family processors, B-155
Pentium 4 processor, B-34, B-55, B-89, B-129
Pentium processors, B-167
reading and writing, 2-26, 2-33, 2-34
reading & writing in 64-bit mode, 2-34
virtualization support, 26-21
VMX support, 26-21
MSR_ TC_PRECISE_EVENT MSR, A-174
MSR_DEBUBCTLB MSR, 18-16, 18-21, 18-36, 18-38
MSR_DEBUGCTLA, 18-29
MSR_DEBUGCTLA MSR, 18-23, 18-26, 18-29, 18-30,
18-32, 18-34, 18-57, 18-62, 18-66,
18-97, B-109
MSR_DEBUGCTLB MSR, 18-15, 18-35, 18-37, B-47,
B-64, B-73, B-140, B-152
MSR_EBC_FREQUENCY_ID MSR, B-93, B-95
MSR_EBC_HARD_POWERON MSR, B-90
MSR_EBC_SOFT_POWERON MSR, B-92
MSR_IFSB_CNTR7 MSR, 18-133
MSR_IFSB_CTRL6 MSR, 18-133
MSR_IFSB_DRDY0 MSR, 18-132
MSR_IFSB_DRDY1 MSR, 18-132
MSR_IFSB_IBUSQ0 MSR, 18-130