Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

18-86 Vol. 3
DEBUGGING AND PERFORMANCE MONITORING
and sampling usages. The event logic unit can filter event counts to specific regions
of code or transaction types incoming to the home node logic.
18.17.2.3 Uncore Address/Opcode Match MSR
The Event Select field [7:0] of MSR_UNCORE_PERFEVTSELx is used to select
different uncore event logic unit. When the event “ADDR_OPCODE_MATCH“ is
selected in the Event Select field, software can filter uncore performance events
according to transaction address and certain transaction responses. The address
filter and transaction response filtering requires the use of
MSR_UNCORE_ADDR_OPCODE_MATCH register. The layout is shown in
Figure 18-34.
• Addr (bits 39:3): The physical address to match if “MatchSel“ field is set to select
address match. The uncore performance counter will increment if the lowest 40-
bit incoming physical address (excluding bits 2:0) for a transaction request
matches bits 39:3.
• Opcode (bits 47:40) : Bits 47:40 allow software to filter uncore transactions
based on QPI link message class/packed header opcode. These bits are consists
two sub-fields:
— Bits 43:40 specify the QPI packet header opcode,
— Bits 47:44 specify the QPI message classes.
Table 18-25 lists the encodings supported in the opcode field.
Figure 18-34. Layout of MSR_UNCORE_ADDR_OPCODE_MATCH MSR
Table 18-25. Opcode Field Encoding for MSR_UNCORE_ADDR_OPCODE_MATCH
Opcode [43:40] QPI Message Class
Home Request
[47:44] = 0000B
Snoop Response
[47:44] = 0001B
Data Response
[47:44] = 1110B
60
MatchSel—Select addr/Opcode
Opcode—Opcode and Message
3
2
0
40 394748
Reserved
ADDR
63
ADDR—Bits 39:4 of physical address
RESET Value — 0x00000000_00000000
Opcode