Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

Vol. 3B Index -23
INDEX
exceptions/interrupts when switching stacks,
5-11
IA-32e mode, 5-25
inter-privilege level calls, 4-25
Stack-fault exception (#SS), 17-40
Stacks
error code pushes, 17-38
faults, 5-48
for privilege levels 0, 1, and 2, 4-26
interlevel RET/IRET
from a 16-bit interrupt or call gate, 17-38
interrupt stack table, 64-bit mode, 5-26
management of control transfers for
16- and 32-bit procedure calls, 16-5
operation on pushes and pops, 17-37
pointers to in TSS, 6-6
stack switching, 4-25, 5-25
usage on call to exception
or interrupt handler, 17-38
Stepping information, following processor
initialization or reset, 8-5
STI instruction, 5-10
Store buffer
caching terminology, 10-8
characteristics of, 10-5
description of, 10-7, 10-29
in IA-32 processors, 17-40
location of, 10-1
operation of, 10-29
STPCLK# pin, 5-4
STR instruction, 2-29, 3-21, 6-9
Strong uncached (UC) memory type
description of, 10-8
effect on memory ordering, 7-23
use of, 8-9, 10-12
Sub C-state, 13-8
SUB instruction, 7-5
Supervisor mode
description of, 4-40
U/S (user/supervisor) flag, 4-40
SVR
Spurious Interrupt Vector Register, 9-23
SVR (spurious-interrupt vector register), local APIC,
9-11, 17-31
SWAPGS instruction, 2-10, 26-23
SYSCALL instruction, 2-10, 4-32, 26-23
SYSENTER instruction, 3-11, 4-14, 4-15, 4-30, 4-31,
26-23
SYSENTER_CS_MSR, 4-30
SYSENTER_EIP_MSR, 4-30
SYSENTER_ESP_MSR, 4-30
SYSEXIT instruction, 3-11, 4-14, 4-15, 4-30, 4-31,
26-23
SYSRET instruction, 2-10, 4-32, 26-23
System
architecture, 2-2, 2-3
data structures, 2-3
instructions
, 2-10, 2-27
registers in IA-32e mode, 2-9
registers, introduction to, 2-9
segment descriptor, layout of, 4-3
segments, paging of, 2-8
System programming
MMX technology, 11-1
SSE/SSE2/SSE3 extensions, 12-1
virtualization of resources, 27-1
System-management mode (see SMM)
T
T (debug trap) flag, TSS, 6-6
Task gates
descriptor, 6-11
executing a task, 6-3
handling a virtual-8086 mode interrupt or
exception through, 15-21
IA-32e mode, 2-7
in IDT, 5-14
introduction for IA-32e, 2-6
introduction to, 2-5, 2-6, 2-7
layout of, 5-14
referencing of TSS descriptor, 5-20
Task management, 6-1
data structures, 6-4
mechanism, description of, 6-3
Task register, 3-21
description of, 2-17, 6-1, 6-9
IA-32e mode, 2-17
initializing, 8-14
introduction to, 2-9
Task switching
description of, 6-3
exception condition, 18-13
operation, 6-13
preventing recursive task switching, 6-18
saving MMX state on, 11-5
saving SSE/SSE2/SSE3 state
on task or context switches, 12-9
T (debug trap) flag, 6-6
Tasks
address space, 6-19
description of, 6-1
exception-handler task, 5-16
executing, 6-3
Intel 286 processor tasks, 17-44
interrupt-handler task, 5-16
interrupts and exceptions, 5-20
linking, 6-16
logical address space, 6-20
management, 6-1
mapping linear and physical address space, 6-19
restart following an exception or interrupt, 5-7
state (context), 6-2, 6-3
structure, 6-1
switching, 6-3
task management data structures, 6-4