Intel 64 and IA-32 Architectures Software Developers Manual Volume 3B, System Programming Guide Part 2

INDEX
Index-24 Vol. 3B
TF (trap) flag, EFLAGS register, 2-12, 5-19, 15-6,
15-29, 18-12, 18-15, 18-26, 18-29,
18-35, 18-37, 18-40, 25-14
Thermal monitoring
advanced power management, 13-8
automatic, 13-11
automatic thermal monitoring, 13-9
catastrophic shutdown detector, 13-9, 13-10
clock-modulation bits, 13-16
C-state, 13-8
detection of facilities, 13-17
Enhanced Intel SpeedStep Technology, 13-1
IA32_APERF MSR, 13-2
IA32_MPERF MSR, 13-2
IA32_THERM_INTERRUPT MSR, 13-17
IA32_THERM_STATUS MSR, 13-17, 13-18
interrupt enable/disable flags, 13-14
interrupt mechanisms, 13-10
MWAIT extensions for, 13-8
on die sensors, 13-10, 13-17
overview of, 13-1, 13-9
performance state transitions, 13-13
sensor interrupt, 9-2
setting thermal thresholds, 13-17
software controlled clock modulation, 13-9, 13-15
status flags, 13-13
status information, 13-13, 13-15
stop clock mechanism, 13-10
thermal monitor 1 (TM1), 13-11
thermal monitor 2 (TM2), 13-11
TM flag, CPUID instruction, 13-17
Thermal status bit, 13-18
Thermal status log bit, 13-18
Thermal threshold #1 log, 13-19
Thermal threshold #1 status, 13-19
Thermal threshold #2 log, 13-19
Thermal threshold #2 status, 13-19
THERMTRIP# interrupt enable bit, 13-20
thread timeout indicator, E-5, E-11, E-15
Threshold #1 interrupt enable bit, 13-21
Threshold #1 value, 13-21
Threshold #2 interrupt enable, 13-21
Threshold #2 value, 13-21
TI (table indicator) flag, segment selector, 3-10
Timer, local APIC, 9-36
Time-stamp counter
counting clockticks, 18-125
description of, 18-42
IA32_TIME_STAMP_COUNTER MSR, 18-42
RDTSC instruction, 18-42
reading, 2-32
software drivers for, 18-147
TSC flag
, 18-42
TSD flag, 18-42
TLBs
description of, 3-23, 10-1, 10-6
flushing, 10-28
invalidating (flushing), 2-31
relationship to PGE flag, 3-33, 17-26
relationship to PSE flag, 3-27, 10-29
TLB shootdown, 7-24
virtual TLBs, 27-5
TM1 and TM2
See: thermal monitoring, 13-11
TMR
Trigger Mode Register, 9-19, 9-23, 9-25, 9-53
TMR (Trigger Mode Register), local APIC, 9-60
TPR
Task Priority Register, 9-19, 9-25
TR (trace message enable) flag
DEBUGCTLMSR MSR, 18-15, 18-26, 18-35, 18-38,
18-40
Trace cache, 10-6
Transcendental instruction accuracy, 17-10, 17-20
Translation lookaside buffer (see TLB)
Trap gates
difference between interrupt and trap gates,
5-19
for 16-bit and 32-bit code modules, 16-2
handling a virtual-8086 mode interrupt or
exception through, 15-18
in IDT, 5-14
introduction for IA-32e, 2-6
introduction to, 2-5, 2-7
layout of, 5-14
Traps
description of, 5-6
restarting a program or task after, 5-7
TS (task switched) flag
CR0 control register, 2-20, 2-30, 5-36, 11-1,
12-4, 12-10
TSD (time-stamp counter disable) flag
CR4 control register, 2-23, 4-34, 17-24, 18-43
TSS
16-bit TSS, structure of, 6-21
32-bit TSS, structure of, 6-4
64-bit mode, 6-22
CR3 control register (PDBR), 6-5, 6-19
description of, 2-5, 2-6, 6-1, 6-4
EFLAGS register, 6-5
EFLAGS.NT, 6-16
EIP, 6-6
executing a task, 6-3
floating-point save area, 17-16
format in 64-bit mode, 6-22
general-purpose registers, 6-5
IA-32e mode, 2-7
initialization for multitasking, 8-14
interrupt stack table, 6-23
invalid TSS exception, 5-42
IRET instruction
, 6-16
I/O map base address field, 6-6, 17-33
I/O permission bit map, 6-6, 6-23
LDT segment selector field, 6-6, 6-19
link field, 5-20
order of reads/writes to, 17-33