Intel Pentium 4 Processor Extreme Edition on 0.13 Micron Process in the 775-Land Package Datasheet

Datasheet 15

Electrical Specifications

2 Electrical Specifications

This chapter describes the electrical characteristics of the processor interfaces and signals. DC

electrical characteristics are provided.

2.1 FSB and GTLREF0

Most processor FSB signals use Gunning Transceiver Logic (GTL+) signaling technology. Pentium

4 processor Extreme Edition in the 775-land package terminates all on-die terminations to V

CC.

must be provided via a separate voltage source and not be connected to V

. This

configuration allows for improved noise tolerance as processor frequency increases. Because of the

speed improvements to data and address bus, signal integrity and platform design methods have

become more critical than with previous processor families. Contact your Intel representative for

details on design guidelines for the Pentium 4 processor Extreme Edition in the 775-land package.

The GTL+ inputs require a reference voltage (GTLREF0) that is used by the receivers to determine

if a signal is a logical 0 or a logical 1. GTLREF0 must be generated on the system board (see

Table 2-13 for GTLREF0 specifications). Termination resistors are provided on the processor

silicon and are terminated to V

. Intel chipsets will also provide on-die termination, thus

eliminating the need to terminate the bus on the system board for most GTL+ signals.

Some GTL+ signals do not include on-die termination and must be terminated on the system board.

The GTL+ bus depends on incident wave switching. Therefore, timing calculations for GTL+

signals are based on flight time as opposed to capacitive deratings. Analog signal simulation of the

FSB, including trace lengths, is highly recommended when designing a system.

2.2 Power and Ground Lands

For clean on-chip power distribution, the Pentium 4 processor Extreme Edition in the 775-land

package has 226 VCC (power), 24 VTT and 273 VSS (ground) lands. All power lands must be

connected to V

, all VTT lands must be connected to V

, while all VSS lands must be connected

to a system ground plane.The processor VCC lands must be supplied the voltage determined by the

VID (Voltage identification) signals.

2.3 Decoupling Guidelines

Due to its large number of transistors and high internal clock speeds, the processor is capable of

generating large current swings between low and full power states. This may cause voltages on

power planes to sag below their minimum values if bulk decoupling is not adequate. Care must be

taken in the board design to ensure that the voltage provided to the processor remains within the

specifications listed in Table 2-5. Failure to do so can result in timing violations or reduced lifetime

of the component. For further information and design guidelines, refer to the Voltage Regulator-

Down (VRD) 10.1 Design Guide for Desktop and Transportable Socket 775.