Intel Pentium 4 Processor Extreme Edition on 0.13 Micron Process in the 775-Land Package Datasheet

20 Datasheet
Electrical Specifications
2.7 GTL+ Asynchronous Signals
The Pentium 4 processor Extreme Edition in the 775-land package does not use CMOS voltage
levels on any signals that connect to the processor. As a result, legacy input signals such as A20M#,
IGNNE#, INIT#, LINT0/INTR, LINT1/NMI, SMI#, SLP#, and STPCLK# use GTL+ input buffers.
Legacy output FERR# and other non-AGTL+ signals (THERMTRIP#) use GTL+ output buffers.
PROCHOT# uses a GTL+ input/output buffer. All of these signals follow the same DC
requirements as AGTL+ signals; however, the outputs are not actively driven high (during a logical
0 to 1 transition) by the processor (the major difference between GTL+ and AGTL+). These signals
do not have setup or hold time specifications in relation to BCLK[1:0]. However, all of the
Asynchronous GTL+ signals are required to be asserted for at least two BCLKs for the processor to
recognize them. See Section 2.11 for the DC characteristics for the Asynchronous GTL+ signal
groups. See Section 6.2 for additional timing requirements for entering and leaving the low power
states.
2.8 Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP) logic, it is
recommended that the Pentium 4 processor Extreme Edition in the 775-land package be first in the
TAP chain and followed by any other components within the system. A translation buffer should be
used to connect to the rest of the chain unless one of the other components is capable of accepting
an input of the appropriate voltage level. Similar considerations must be made for TCK, TMS,
TRST#, TDI, and TDO. Two copies of each signal may be required, with each driving a different
voltage level.
2.9 FSB Frequency Select Signals (BSEL[2:0])
The BSEL[2:0] signals are used to select the frequency of the processor input clock (BCLK[1:0]).
Table 2-3 defines the possible combinations of the signals and the frequency associated with each
combination. The required frequency is determined by the processor, chipset, and clock
synthesizer. All agents must operate at the same frequency.
The Pentium 4 processor Extreme Edition in the 775-land package currently operates at a 800 MHz
FSB frequency (selected by a 200 MHz BCLK[1:0] frequency). Individual processors will only
operate at their specified FSB frequency. For more information about these signals, refer to
Section 4.2.
Table 2-3. BSEL[2:0] FSB Frequency Selections
BSEL2 BSEL1 BSEL0 Function
L H L 200 MHz
L H L 266 MHz