Intel Pentium 4 Processor on 90 nm Process
Datasheet 27
Electrical Specifications
Table 12. GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage 0.0 GTLREF – (0.10 * V
CC
)V
2, 3
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. The V
CC
referred to in these specifications is the instantaneous V
CC
.
V
IH
Input High Voltage GTLREF + (0.10 * V
CC
)V
CC
V
3, 4
4. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
V
OH
Output High Voltage 0.90*V
CC
V
CC
V
3
I
OL
Output Low Current N/A V
CC
/[(0.50*R
TT_MIN
)+(R
ON_MIN
)] A
I
LI
Input Leakage Current N/A ± 200 µA
5
5. Leakage to V
SS
with pin held at V
CC
.
I
LO
Output Leakage Current N/A ± 200 µA
6
6. Leakage to V
CC
with pin held at 300 mV.
R
ON Buffer On Resistance 8 12 Ω
Table 13. Asynchronous GTL+ Signal Group DC Specifications
Symbol Parameter Min Max Unit Notes
1
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
V
IL
Input Low Voltage 0.0 V
CC
/2 – (0.10 * V
CC
)V
2, 3
2. V
IL
is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
3. LINT0/INTR and LINT1/NMI use GTLREF as a reference voltage. For these two signals,
V
IH
= GTLREF + (0.10 * V
CC
) and V
IL
= GTLREF - (0.10 * Vcc).
V
IH
Input High Voltage V
CC
/2 + (0.10 * V
CC
)V
CC
V
3, 4, 5
4. V
IH
is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5. The V
CC
referred to in these specifications refers to instantaneous V
CC
.
V
OH
Output High Voltage 0.90*V
CC
V
CC
V
5, 6
6. All outputs are open drain.
I
OL
Output Low Current V
CC
/[(0.50*R
TT_MIN
)+(R
ON_MIN
)] A
7
7. The maximum output current is based on maximum current handling capability of the buffer and is not specified into
the test load.
I
LI
Input Leakage Current N/A ± 200 µA
8
8. Leakage to Vss with pin held at V
CC
.
I
LO
Output Leakage Current N/A ± 200 µA
10
RON Buffer On Resistance 8 12 Ω