Intel Pentium 4 Processor on 90 nm Process

Datasheet 71
Features
6 Features
This chapter contains power-on configuration options and clock control/low power state
descriptions.
6.1 Power-On Configuration Options
Several configuration options can be configured by hardware. The processor samples the hardware
configuration at reset, on the active-to-inactive transition of RESET#. For specifications on these
options, refer to Table 30.
The sampled information configures the processor for subsequent operation. These configuration
options cannot be changed except by another reset. All resets reconfigure the processor; for reset
purposes, the processor does not distinguish between a "warm" reset and a "power-on" reset.
Table 30. Power-On Configuration Option Pins
Configuration Option Pin
1
,
2
NOTES:
1. Asserting this signal during RESET# will select the corresponding option.
2. Address pins not identified in this table as configuration options should not be asserted during RESET#.
Output tristate SMI#
Execute BIST INIT#
In Order Queue pipelining (set IOQ depth to 1) A7#
Disable MCERR# observation A9#
Disable BINIT# observation A10#
APIC Cluster ID (0-3) A[12:11]#
Disable bus parking A15#
Disable Hyper-Threading Technology A31#
Symmetric agent arbitration ID BR0#
RESERVED A[6:3]#, A8#, A[14:13]#, A[16:30]#, A[32:35]#