Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
Page 23
The various output current configurations are shown in the appendix of this document. For all
configurations, the deviation from the expected output current is +/- 7% as shown in Table 3.8.
Table 3.8 – Current Accuracy
Conditions Configuration Load
Min
Max
Iout
Vdd = nominal (3.30V) All combinations of M0, M1
and Rr shown in Table 6.9
Nominal test load for
given configuration
-7% I
nominal
+7% I
nominal
Iout
Vdd = 3.30 +/- 5% All combinations of M0, M1
and Rr shown in Table 6.9
Nominal test load for
given configuration
-12% I
nominal
+12% I
nominal
Note: I
nominal
refers to the expected current based on the configuration of the device.