Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
Page 31
6. Appendices
6.1 Pin-outs and Features
The following addendum defines a generic pin-out and base requirements for Intel
Architecture based platforms. It is intended to be used with another clock driver or
drivers to clock the memory devices.
CKx_SKS clock chip (56 SSOP and 56 TSSOP):
Description: This clock is intended to be used in single processor systems and two processor
systems.
!
Four Differential Host Clock Pairs
!
Two 3V Single Ended memory reference clocks 180 degrees out of phase
!
Four 3V, 66MHz Clocks
!
Ten 3V, 33MHz PCI Clocks
!
Two 48MHz Clocks
!
Two 14.318MHz Reference Clocks
!
Select logic for Differential Swing Control, Test mode, Hi-Z, Power-down, Spread spectrum,
limited frequency select, and other
!
External resistor for current reference
GndR 1 56 3.3M
Ref/MultSel0* 2 55 3VMref
Ref/MultSel1* 3 54 3VMref_b
3.3R 4 53 GndM
Xtal_in 5 52 Spread#
Xtal_out 6 51 Host
GndP 7 50 Host_bar
PCI 8 49 3.3H
PCI 9 48 Host
3.3P 10 47 Host_bar
PCI 11 46 GndH
PCI 12 SKS 45 Host
GndP 13 44 Host_bar
PCI 14 43 3.3H
PCI 15 42 Host
3.3P 16 41 Host_bar
PCI 17 40 GndH
PCI 18 39 I Ref
GndP 19 38 3.3Core
PCI 20 37 GndCore
PCI 21 36 3.3L
3.3P 22 35 3V66
Sel100/133 23 34 3V66
GndU 24 33 GndL
48MHz/SelA 25 32 GndL
48MHz/SelB 26 31 3V66
3.3U 27 30 3V66
PWRDWN# 28 29 3.3L