Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
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CKx_RGR clock chip Future pin-out (48 TSSOP and 48 SSOP):
Description: This clock is intended as a future spin of the SKS. This clock is intended for single
processor platforms.
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Two Differential Host Clock Pairs
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Two 3V Single Ended memory reference clocks 180 degrees out of phase
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Three 3V, 66MHz Clocks
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Ten 3V, 33MHz PCI Clocks
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Two 48MHz Clocks
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Two 14.318MHz Reference Clocks
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Select logic for Differential Swing Control, Test mode, Hi-Z, Power-down, Spread spectrum,
limited frequency select, and other
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External resistor for current reference
Ref/MultSel1* 1 48 Ref/MultSel0*
3.3R 2 47 GndR
Xtal_in 3 46 3.3M
Xtal_out 4 45 3VMref
GndP 5 44 3VMref_b
PCI 6 43 GndM
PCI 7 42 Spread#
3.3P 8 41 Host
PCI 9 40 Host_bar
PCI 10 RGR 39 3.3H
GndP 11 38 Host
PCI 12 37 Host_bar
PCI 13 36 GndH
3.3P 14 35 I Ref
PCI 15 34 3.3Core
PCI 16 33 GndCore
GndP 17 32 PWRDWN#
PCI 18 31 3.3L
PCI 19 30 3V66
3.3P 20 29 3V66
Sel100/133 21 28 GndL
GndU 22 27 3V66
48MHz/SelA 23 26 3.3L
48MHz/SelB 24 25 3.3U