Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
Page 4
1. INTRODUCTION ...................................................................................................6
1.1 Clock Synthesizer Overview ...........................................................................................................6
1.2 Applicable Documents.....................................................................................................................6
1.3 Drive Specification...........................................................................................................................7
2. EXAMPLE CIRCUITS............................................................................................9
2.1 Current Reference and Mirror Circuit.............................................................................................9
2.2 System Implementation.................................................................................................................11
2.2.1 Source termination of differential HCSL type outputs..............................................................11
2.2.2 Pull-ups/Pull-down resistors for latched inputs........................................................................13
3. ELECTRICAL REQUIREMENTS ........................................................................14
3.1 DC Specifications...........................................................................................................................14
3.1.1 Load Capacitance As Seen By External Crystal Reference ....................................................16
3.2 Buffer Specifications:....................................................................................................................17
3.2.1 TYPE 3: Buffer Characteristics................................................................................................18
3.2.2 TYPE 5: Buffer Characteristics................................................................................................19
3.2.3 Type X1 Current-mode Output Buffer Characteristics.............................................................22
4. AC TIMING..........................................................................................................24
4.1 Timing Requirements ....................................................................................................................24
4.1.1 Frequency Accuracy of 48MHz outputs...................................................................................26
4.1.2 Multiple PLL Jitter Tracking Specification................................................................................27
5. TEST AND MEASUREMENT..............................................................................28
6. APPENDICES .....................................................................................................31
6.1 Pin-outs and Features ...................................................................................................................31
6.2 Select Pin Logic .............................................................................................................................39
6.3 Spread Spectrum Clocking (SSC) Criteria:..................................................................................44
6.4 Non-production Frequencies for System Debug........................................................................47
6.5 PWRDWN# Mode............................................................................................................................47
6.6 Package Data..................................................................................................................................48