Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
Page 41
Table 6.7 Select Functions –
CKx_WBY
SEL100/133 SELA SELB Function
0 0 0 Active 100MHz
0 0 1 Active 100MHz, ref_out Low, 66_out
Low, 3VMRef and 3VMRef_b Low
0 1 0 (Reserved)
0 1 1 HI-Z all outputs
1 0 0 Active 133MHz
1 0 1 (Reserved)
1 1 0 (Reserved)
111Test Mode
SEL
100/133
SELA SELB Host MRef 66M
seed
14.318M
seed
Notes:
0 0 0 100MHz 50MHz 66MHz 14.318MHz
001
100MHz Low Low Low
0 1 0 N/A N/A N/A N/A
0 1 1 HI-Z HI-Z HI-Z HI-Z
1 0 0 133MHz 66MHz 66MHz 14.318MHz
1 0 1 N/A N/A N/A N/A
1 1 0 N/A N/A N/A N/A
1 1 1 TCLK/2 TCLK/4 TCLK TCLK