Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
Page 47
6.4 Non-production Frequencies for System Debug
Some system debug applications exist where CPU frequencies that are above and below the
specified 100, 133 MHz are of interest for this device. The ability to use this device in a lab
environment using a 10 or 20 MHz crystal is desired. Another desired feature of this product is
the ability to use a function generator (in lab environment only) to drive XTAL_IN (float
XTAL_OUT) in test mode to create the frequencies shown in the selection table for Test Mode.
6.5 PWRDWN# Mode
When PWRDWN# is asserted, a voltage must be held across the differential outputs.
PWRDWN# Host / Host_bar Mref /
Mref_b
3V66 PCI 48MHz Ref 14.318, 66
seeds
Asserted =
0 = low
Host = 2*Iref
Host_bar = undriven
Low Low Low Low Low Low
(if applicable)
There are no specific timing requirements for entering or exiting PWRDWN# mode.