Intel Pentium 4 Processor CK00 Clock Synthesizer/Driver Design Guidelines

CK00 Clock Synthesizer/Driver Design Guidelines
Page 53
Byte 0 : CKFF Active/Inactive Register (1 = enable, 0 = disable)
Bit Name Description
Bit 7 PCI0 (Active/Inactive)
Bit 6 PCI1 (Active/Inactive)
Bit 5 PCI2 (Active/Inactive)
Bit 4 PCI3 (Active/Inactive)
Bit 3 PCI4 (Active/Inactive)
Bit 2 PCI5 (Active/Inactive)
Bit 1 PCI6 (Active/Inactive)
Bit 0 PCI7 (Active/Inactive)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation,
Byte 1 : CKFF Active/Inactive Register (1 = enable, 0 = disable)
Bit Name Description
Bit 7 PCI8 (Active/Inactive)
Bit 6 PCI9 (Active/Inactive)
Bit 5 PCI10 (Active/Inactive)
Bit 4 PCI11 (Active/Inactive)
Bit 3 48M0 (Active/Inactive)
Bit 2 48M1 (Active/Inactive)
Bit 1 14M0 (Active/Inactive)
Bit 0 14M1 (Active/Inactive)
Notes:
2. Inactive means outputs are held LOW and are disabled from switching. These outputs are designed to be
configured at power-on and are not expected to be configured during the normal modes of operation,
Byte 2 : CKFF Active/Inactive Register (1 = enable, 0 = disable)
Bit Name Description
Bit 7 66M0 (Active/Inactive)
Bit 6 66M1 (Active/Inactive)
Bit 5 66M2 (Active/Inactive)
Bit 4 66M3 (Active/Inactive)
Bit 3 66M4 (Active/Inactive)
Bit 2 66M5 (Active/Inactive)
Bit 1 (Reserved for Intel)
Bit 0 (Reserved for Intel)