CK00 Clock Synthesizer/Driver Design Guidelines
Page 8
Figure 1.1 – One and Two Chip Solutions
CKx_SKS
Divide
by
Two
3V66s
PLL
PLL
Diff Clks
PCIs
Mref
Seed
Clks
14.318, 48
CKx_WBY
CKFF
Differential Hosts
14M
Mref, Mref_b
66M reference
Divide
by
Two
3V66’s
33MHz PCI’s
PLL
14.318, 48
14.318MHz seed
66MHz seed
