Intel Pentium 4 Processor Extreme Edition on 0.13 Micron Process in the 775-Land Package Datasheet

12 Datasheet
Introduction
The Streaming SIMD Extensions 2 (SSE2) enable break-through levels of performance in
multimedia applications including 3-D graphics, video decoding/encoding, and speech recognition.
The new packed double-precision floating-point instructions enhance performance for applications
that require greater range and precision, including scientific and engineering applications and
advanced 3-D geometry techniques, such as ray tracing.
The 2-MB L3 cache is available with the Pentium 4 processor Extreme Edition in the 775-land
package. The additional third level of cache is located on the processor die and is designed
specifically to meet the compute needs of high-end gamers and other power users. The integrated
L3 cache is available in 2-MB and is coupled with the 800 MHz or 1066 MHz system bus to
provide a high bandwidth path to memory. The efficient design of the integrated L3 cache provides
a faster path to large data sets stored in cache on the processor. This results in reduced average
memory latency and increased throughput for larger workloads.
The processor’s Intel NetBurst microarchitecture front side bus (FSB) uses a split-transaction,
deferred reply protocol like the Pentium 4 processor. The Intel NetBurst microarchitecture FSB
uses Source-Synchronous Transfer (SST) of address and data to improve performance by
transferring data four times per bus clock (4X data transfer rate, as in AGP 4X). Along with the 4X
data bus, the address bus can deliver addresses two times per bus clock and is referred to as a
“double-clocked” or 2X address bus. Working together, the 4X data bus and 2X address bus
provide a data bus bandwidth of up to 8.5 GB/sec.
Intel will enable support components for the processor including heatsink, heatsink retention
mechanism, and socket. Manufacturability is a high priority; hence, mechanical assembly may be
completed from the top of the baseboard and should not require any special tooling.
The processor includes an address bus powerdown capability that removes power from the address
and data pins when the FSB is not in use. This feature is always enabled on the processor.
1.1 Terminology
A ‘#’ symbol after a signal name refers to an active low signal, indicating a signal is in the active
state when driven to a low level. For example, when RESET# is low, a reset has been requested.
Conversely, when NMI is high, a nonmaskable interrupt has occurred. In the case of signals where
the name does not imply an active state but describes part of a binary sequence (such as address or
data), the ‘#’ symbol implies that the signal is inverted. For example, D[3:0] = ‘HLHL’ refers to a
hex ‘A’, and D[3:0]# = ‘LHLH’ also refers to a hex ‘A’ (H= High logic level, L= Low logic level).
“FSB” refers to the interface between the processor and system core logic (a.k.a. the chipset
components). The FSB is a multiprocessing interface to processors, memory, and I/O.