Intel Pentium 4 Processor Extreme Edition on 0.13 Micron Process in the 775-Land Package Datasheet

Datasheet 17

Electrical Specifications

2.4.1 Phase Lock Loop (PLL) Power and Filter

CCA

and V

CCIOPLL

are power sources required by the PLL clock generators on the Pentium 4

processor Extreme Edition in the 775-land package. Since these PLLs are analog, they require low

noise power supplies for minimum jitter. Jitter is detrimental to the system: it degrades external I/O

timings as well as internal core timings (i.e., maximum frequency). To prevent this degradation,

these supplies must be low pass filtered from V

Note: The PLL filter for the Pentium 4 Extreme Edition in the 775-land package has been

implemented inside the package. The VSSA, VCCA, and VCCIOPLL lands are not

connected for this processor. These signals are used for compatible processors. For further

details, contact your Intel representative.

2.5 Reserved, Unused, and TESTHI Signals

All RESERVED signals must remain unconnected. Connection of these signals to V

, V

TT,

or to any other signal (including each other) can result in component malfunction or

incompatibility with future processors. See Chapter 4 for a land listing of the processor and the

location of all RESERVED signals.

For reliable operation, always connect unused inputs or bidirectional signals to an appropriate

signal level. In a system level design, on-die termination has been included on the Pentium 4

processor Extreme Edition in the 775-land package to allow signals to be terminated within the

processor silicon. Most unused GTL+ inputs should be left as no connects, as GTL+ termination is

provided on the processor silicon. Unused active high inputs should be connected through a resistor

to ground (V

). Unused outputs can be left unconnected, however this may interfere with some

test access port (TAP) functions, complicate debug probing, and prevent boundary scan testing. A

resistor must be used when tying bi-directional signals to power or ground. When tying any signal

to power or ground, a resistor will also allow for system testability. For unused GTL+ input or I/O

signals, use pull-up resistors of the same value as the on-die termination resistors (R

). See

Table 2-13.

TAP, GTL+ Asynchronous inputs, and GTL+ Asynchronous outputs do not include on-die

termination. Inputs and used outputs must be terminated on the system board. Unused outputs may

be terminated on the system board or left unconnected. Note that leaving unused outputs

unterminated may interfere with some TAP functions, complicate debug probing, and prevent

boundary scan testing. For further information on termination for these signal types contact your

Intel representative.

The TESTHI[12:1] signals must be tied to the processor’s appropriate power source (refer to the

VTT_OUT_LEFT and VTT_OUT_RIGHT signal description in Chapter 4) using a matched

resistor, where a matched resistor has a resistance value within 20% of the impedance of the board

transmission line traces. For example, if the trace impedance is 60 Ω, a value between 48 Ω and

72 Ω is required. For TESTHI0 termination recommendations contact your Intel representative for

further details and documentation.