Manualshelf

Intel Pentium 4 Processor in the 478-pin Package / Intel 850 Chipset Platform Family Design Guide

ManualsBrandsIntel ManualsOtherIntel Pentium 4 Processor supporting HT Technology 3.00E GHz, 1M Cache, 800 MHz FSB
101102103104105106107108109110
Memory Interface Routing
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 101
Figure 63. Bottom Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 1.35 pF)
The CTAB can be implemented on the multiple layers to minimize routing and space constrains.
Figure 64 issues the use of CTABs on the top and bottom layer for bottom layer RSL and clocking
signals routed between RIMM connectors.
Figure 64. Bottom Layer CTABs Split Across the Top and Bottom Layer to Achieve an Effect
Ceff ~1.35 pF