Intel Pentium 4 Processor in the 478-pin Package / Intel 850 Chipset Platform Family Design Guide

Platform Clock Routing Guidelines
R
40 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
Figure 11. Clocking Architecture Using the CK00
CPU
BCLK[0]
BCLK[1]
Debug Port
BCLK[0]
BCLK[1]
MCH
ICH2
AGP
Connector
PCI
Connectors
Glue Chip
SIO
FWH
100 MHz
100 MHz
100 MHz
100 MHz
100 MHz
66IN
BCLK[0]
BCLK[1]
CLK
100 MHz
66 MHz
66 MHz
66 MHz
33 MHz
48 MHz
33 MHz
14.318 MHz
33 MHz
CLK66
PCICLK
CLK48
APICCLK
CLK14
33 MHz
33 MHz
33 MHz
14.318 MHz
33 MHz
33 MHz
CLK
CLOCKI
PCI_CLK
CLK_IN
CLK CLK CLK
CK00
CPU#
CPU
CPU#
CPU#
CPU
CPU
66
66
66
PCIF
USB
PCIF
PCI
PCI
PCI
REFO
PCI
PCI
PCI
Clk_Arch_Ck00