Intel Pentium 4 Processor in the 478-PinPackage at 1.40 GHz, 1.50 GHz, 1.60 GHz, 1.70 GHz, 1.80 GHz, 1.90 GHz, and 2GHz
Electrical Specifications
26 Datasheet
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor core frequencies.
2. The period specified here is the average period. A given period may vary from this specification as governed
by the period stability specification (T2).
3. For the clock jitter specification, refer to the CK00 Clock Synthesizer/Driver Design Guidelines.
4. In this context, period stability is defined as the worst case timing difference between successive crossover
voltages. In other words, the largest absolute difference between adjacent clock periods must be less than
the period stability.
5. Slew rate is measured between the 35% and 65% points of the clock swing (V
L
to V
H
).
.
NOTES:
1. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2. Not 100% tested. Specified by design characterization.
3. All common clock AC timings for AGTL+ signals are referenced to the Crossing Voltage (V
CROSS
)ofthe
BCLK[1:0] at rising edge of BCLK0. All common clock AGTL+ signal timings are referenced at GTLREF at the
processor core.
4. Valid delay timings for these signals are specified into the test circuit described in Figure 4 and with GTLREF
at 2/3 V
CC
±2%.
5. Specification is for a minimum swing defined between AGTL+ V
IL_MAX
to V
IH_MIN
. This assumes an edge rate
of 0.4 V/ ns to 4.0V/ns.
6. RESET# can be asserted asynchronously, but must be deasserted synchronously.
7. This should be measured after V
CC
and BCLK[1:0] become stable.
8. Maximum specification applies only while PWRGOOD is asserted.
.
Table 13. System Bus Differential Clock Specifications
T# Parameter Min Nom Max Unit Figure Notes
1
System Bus Frequency 100 MHz
T1: BCLK[1:0] Period 10.0 10.2 ns 6 2
T2: BCLK[1:0] Period Stability 200 ps 6 3, 4
T3: BCLK[1:0] High Time 3.94 5 6.12 ns 6
T4: BCLK[1:0] Low Time 3.94 5 6.12 ns 6
T5: BCLK[1:0] Rise Time 175 700 ps 6 5
T6: BCLK[1:0] Fall Time 175 700 ps 6 5
Table 14. System Bus Common Clock AC Specifications
T# Parameter Min Max Unit Figure Notes
1,2,3
T10: Common Clock Output Valid Delay 0.200 1.45 ns 8 4
T11: Common Clock Input Setup Time 0.65 N/A ns 8 5
T12: Common Clock Input Hold Time 0.40 N/A ns 8 5
T13: RESET# Pulse Width 1.00 10.00 ms 9 6, 7, 8