Intel Pentium 4 Processor in the 478-PinPackage at 1.40 GHz, 1.50 GHz, 1.60 GHz, 1.70 GHz, 1.80 GHz, 1.90 GHz, and 2GHz

Electrical Specifications
32 Datasheet
Figure 8. System Bus Common Clock Valid Delay Timings
Figure 9. System Bus Reset and Configuration Timings
BCLK0
BCLK1
Common Clock
Signal (@ driver)
Common Clock
Signal (@ receiver)
T0
T1 T2
T
Q
T
R
valid valid
valid
T
P
T
P
=T10:T
CO
(Data Valid Output Delay)
T
Q
=T11:T
SU
(Common Clock Setup)
T
R
= T12: T
H
(Common Clock Hold Time)
BCLK
RESET#
Configuration
(A[31:3], BR0#,
INIT#, SMI#)
Tv
Tw Tx
Tv = T13 (RESET# Pulse Width)
Tw = T45 (Reset Configuration Signals Setup Time)
Tx = T46 (Reset Configuration Signals Hold Time)