Intel Pentium 4 Processor in the 478-PinPackage at 1.40 GHz, 1.50 GHz, 1.60 GHz, 1.70 GHz, 1.80 GHz, 1.90 GHz, and 2GHz

System Bus Signal Quality Specifications
Datasheet 39
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all Pentium® 4 processor in the 478-pin
package frequencies and cache sizes.
3. Specifications are for the edge rate of 0.3 - 4.0V/ns.
4. All values specified by design characterization.
5. Please see Section 3.3 for maximum allowable overshoot.
6. Ringback between GTLREF + 100 mV and GTLREF - 100 mV is not supported.
7. Intel recommends simulations not exceed a ringback value of GTLREF +/- 200 mV to allow margin for other
sources of system noise.
NOTES:
1. All signal integrity specifications are measured at the processor silicon.
2. Unless otherwise noted, all specifications in this table apply to all processor frequencies.
3. Please see Section 3.3 for maximum allowable overshoot.
4. Please see Section 2.11 for the DC specifications.
Table 20. Ringback Specifications for AGTL+ and Asynchronous GTL+ Signal Groups
Signal Group Transition
Maximum Ringback
(with Input Diodes Present) Unit Figure
Notes
All Signals 0 → 1 GTLREF + 0.100 V 17 1,2,3,4,5,6,7
All Signals 1 → 0 GTLREF - 0.100 V 18 1,2,3,4,5,6,7
Table 21. Ringback Specifications for PWRGOOD and TAP Signal Group
Signal Group Transition
Maximum Ringback
(with Input Diodes Present) Unit Figure
Notes
TAP 0 → 1V
t+(max) TO Vt-(max) V 19 1,2,3,4
TAP 1 → 0V
t-(min) TO Vt+(min) V 20 1,2,3,4
Figure 17. Low-to-High System Bus Receiver Ringback Tolerance
GTLREF
V
CC
Noise Margin
+100 mV
-100 mV
V
SS