Intel Pentium 4 Processor in the 478-PinPackage at 1.40 GHz, 1.50 GHz, 1.60 GHz, 1.70 GHz, 1.80 GHz, 1.90 GHz, and 2GHz

Features
84 Datasheet
If RESET# is driven active while the processor is in the Sleep state, and held active as
specified in the RESET# pin specification, then the processor will reset itself, ignoring the
transition through Stop-Grant State. If RESET# is driven active while the processor is in
the Sleep State, the SLP# and STPCLK# signals should be deasserted immediately after
RESET# is asserted to ensure the processor correctly executes the Reset sequence.
While in the Sleep state, the processor is capable of entering its lowest power state, the
Deep Sleep state, by stopping the BCLK[1:0] inputs. (See Section 7.2.6). Once in the
Sleep or Deep Sleep states, the SLP# pin must be de-asserted if another asynchronous
system bus event needs to occur. The SLP# pin has a minimum assertion of one BCLK
period.
When the processor is in Sleep state, it will not respond to interrupts or snoop
transactions.
7.2.6 Deep Sleep State—State 6
Deep Sleep state is the lowest power state the processor can enter while maintaining
context. Deep Sleep state is entered by stopping the BCLK[1:0] inputs (after the Sleep
state was entered from the assertion of the SLP# pin). The processor is in Deep Sleep
state immediately after BLCK[1:0] is stopped. To provide maximum power conservation
hold the BLCK0 input at V
OL
and the BCLK1 input at V
OH
during the Deep Sleep state.
Stopping the BCLK input lowers the overall current consumption to leakage levels.
To re-enter the Sleep state, the BLCK input must be restarted. A period of 1 ms (to allow
for PLL stabilization) must occur before the processor can be considered to be in the
Sleep State. Once in the Sleep state, the SLP# pin can be deasserted to re-enter the
Stop-Grant state.
While in Deep Sleep state, the processor is incapable of responding to snoop transactions
or latching interrupt signals. No transitions or assertions of signals are allowed on the
system bus while the processor is in Deep Sleep state. Any transition on an input signal
before the processor has returned to Stop-Grant state will result in unpredictable
behaviour. The processor has to stay in Deep Sleep mode for minimum of 25 µs.
When the processor is in Deep Sleep state, it will not respond to interrupts or snoop
transactions.
7.3 Thermal Monitor
The Thermal Monitor feature found in the Pentium 4 processor in the 478-pin package
allows system designers to design lower cost thermal solutions without compromising
system integrity or reliability. By using a factory-tuned, precision on-die thermal sensor,
and a fast acting thermal control circuit (TCC), the processor, without the aid of any
additional software or hardware, can keep the processor’s die temperature within factory
specifications under nearly all conditions. Thermal Monitor thus allows the processor and
system thermal solutions to be designed much closer to the power envelopes of real
applications, instead of being designed to the much higher maximum processor power
envelopes.