Intel Pentium 4 Processor on 90 nm Process

Summary Tables of Changes
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update 13
NO. C0
1
D0 LD0
2
E0 LE0
2
G1
1
LG1
2
LN0
2
LR0
2
Plan ERRATA
R54 X5 X X Fixed
WRMSR to bit[0] of
IA32_MISC_ENABLE Register
Changes Only One Logical
Processor on a Hyper-Threading
Technology Enabled Processor
R55 X5 X5 X X Fixed
VERR/VERW Instructions May
Cause #GP Fault when Descriptor
is in Non-canonical Space
R56 X X Fixed
The Base of a Null Segment May
be Non-zero on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)Φ
R57 X X Fixed
Upper 32 Bits of FS/GS with Null
Base May not get Cleared in
Virtual-8086 Mode on Processors
with Intel® Extended Memory 64
Technology (Intel® EM64T)
Enabled
R58 X X X X X
No
Fix
Processor May Fault when the
Upper 8 Bytes of Segment Selector
is Loaded From a Far Jump
Through a Call Gate via the Local
Descriptor Table
R59 X X X X X
No
Fix
Loading a Stack Segment with a
Selector that References a Non-
canonical Address can Lead to a
#SS Fault on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R60 X X X X X
No
Fix
FXRSTOR May Not Restore Non-
canonical Effective Addresses on
Processors with Intel® Extended
Memory 64 Technology (Intel®
EM64T) Enabled
R61 X X X X X
No
Fix
A Push of ESP that Faults may
Zero the Upper 32 Bits of RSP
R62 X Fixed
Enhanced Halt State (C1E) Voltage
Transition May Affect a System’s
Power Management in a Hyper-
Threading Technology
Enabled Processor
R63 X X X X
No
Fix
Enhanced Halt State (C1E) May
Not Be Entered in a Hyper-
Threading Technology Enabled
Processor
R64 X Fixed
When the Execute Disable Bit
Function is Enabled a Page-fault in
a Mispredicted Branch May Result
in a Page-fault Exception