Intel Pentium 4 Processor on 90 nm Process

Summary Tables of Changes
R
14 Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update
NO. C0
1
D0 LD0
2
E0 LE0
2
G1
1
LG1
2
LN0
2
LR0
2
Plan ERRATA
R65 X Fixed
Execute Disable Bit Set with AD
Assist Will Cause Livelock
R66 X Fixed
The Execute Disable Bit Fault May
be Reported Before Other Types
of Page Fault When Both Occur
R67 X Fixed
Writes to IA32_MISC_ENABLE May
Not Update Flags for Both Logical
Processors Threads
R68 X Fixed
Execute Disable Mode Bit Set with
CR4.PAE May Cause Livelock
R69 X X X X X X X X X
No
Fix
Checking of Page Table Base
Address May Not Match the
Address Bit Width Supported by the
Platform
R70 X X X X X X X X X
No
Fix
The IA32_MCi_STATUS MSR May
Improperly Indicate that Additional
MCA Information May Have Been
Captured
R71 X Fixed
Execution of an Instruction with a
Code Breakpoint Inhibited by the
RF (Resume Flag) Bit May be
Delayed by an RFO (Request For
Ownership) from Another Bus
Agent
R72 X X X X X X X X X
No
Fix
With TF (Trap Flag) Asserted, FP
Instruction That Triggers an
Unmasked FP Exception May Take
Single Step Trap Before Retirement
of Instruction
R73 X X X Fixed
MCA Corrected Memory Hierarchy
Error Counter May Not Increment
Correctly
R74 X X X X X X X X X
No
Fix
BTS(Branch Trace Store) and
PEBS(Precise Event Based
Sampling) May Update Memory
outside the BTS/PEBS Buffer
R75 X X X X Fixed
The Base of an LDT (Local
Descriptor Table) Register May be
Non-zero on a Processor
Supporting Intel® Extended
Memory 64 Technology (Intel®
EM64T)
R76 X X X Fixed
L-bit of the CS and LMA bit of the
IA32_EFER Register May Have an
Erroneous Value For One
Instruction Following a Mode
Transition in a Hyper-Threading
Enabled Processor Supporting
Intel® Extended Memory 64
Technology (Intel® EM64T).