Intel Pentium 4 Processor on 90 nm Process

Errata
R
Intel
®
Pentium
®
4 Processor on 90 nm Process Specification Update 51
R59. Loading a Stack Segment with a Selector that References a Non-canonical
Address Can Lead to a #SS Fault on a Processor Supporting Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Problem: When a processor supporting Intel EM64T is in IA-32e mode, loading a stack segment with a
selector which references a non-canonical address will result in a #SS fault instead of a #GP fault.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter unexpected behavior.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.
R60. FXRSTOR May Not Restore Non-canonical Effective Addresses on
Processors with Intel
®
Extended Memory 64 Technology (Intel
®
EM64T)
Enabled
Problem: If an x87 data instruction has been executed with a non-canonical effective address, FXSAVE
may store that non-canonical FP Data Pointer (FDP) value into the save image. An FXRSTOR
instruction executed with 64-bit operand size may signal a General Protection Fault (#GP) if the
FDP or FP Instruction Pointer (FIP) is in non-canonical form.
Implication: When this erratum occurs, Intel EM64T enabled systems may encounter an unintended #GP fault.
Workaround: Software should avoid using non-canonical effective addressing in EM64T enabled processors.
BIOS can contain a workaround for this erratum removing the unintended #GP fault on
FXRSTOR.
Status: For the steppings affected, see the Summary Tables of Changes.
R61. A Push of ESP That Faults May Zero the Upper 32 Bits of RSP
Problem: In the event that a push ESP instruction, that faults, is executed in compatibility mode, the
processor will incorrectly zero upper 32-bits of RSP.
Implication: A Push of ESP in compatibility mode will zero the upper 32-bits of RSP. Due to this erratum,
this instruction fault may change the contents of RSP. This erratum has not been observed in
commercially available software.
Workaround: None identified.
Status: For the steppings affected, see the Summary Tables of Changes.