Intel Pentium 4 Processor Specification Update

Summary Tables of Changes
20 Specification Update
No. B2 C1 D0 E0 B0 C1 D1 M0 Plan ERRATA
when an Interrupt is Pending May Cause an
Unexpected Interrupt
N102 X X X X X X X X No Fix
Using 2M/4M Pages When A20M# Is
Asserted May Result in Incorrect
Address Translations
N103 X X X X X X X X No Fix
Writing Shared Unaligned Data that
Crosses a Cache Line without Proper
Semaphores or Barriers May Expose a
Memory Ordering Issue
N104 X X X X X X X X No Fix
Debug Status Register (DR6)
Breakpoint Condition Detected Flags
May be set Incorrectly
NOTE:
1. For these steppings, this erratum may be worked around in BIOS.
No. B2 C1 D0 E0 B0 C1 D1 M0 Plans SPECIFICATION CHANGES
There are no specification changes in
this Specification Update revision.
No. B2 C1 D0 E0 B0 C1 D1 M0 Plans SPECIFICATION CLARIFICATIONS
N1 X X X X X X X X Doc
Specification clarification with respect
to time stamp counter
No. B2 C1 D0 E0 B0 C1 D1 M0 Plans DOCUMENTATION CHANGES
There are no Documentation Changes
in this Specification Update revision.
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