Intel Pentium 4 Processor Specification Update

Errata
Specification Update 49
48. Bus Invalidate Line Requests That Return Unexpected Data May
Result in L1 Cache Corruption
Problem: When a Bus Invalidate Line (BIL) request receives unexpected data from a deferred
reply, and a store operation write combines to the same address, there is a small
window where the L0 is corrupt, and loads can retire with this corrupted data. This
erratum occurs in the following scenario
• A Read-For-Ownership (RFO) transaction is issued by the processor and hits a
line in shared state in the L1 cache.
• The RFO is then issued on the system bus as a 0 length Read-Invalidate (a BIL),
since it doesn't need data, just ownership of the cache line.
• This transaction is deferred by the chipset.
• At some later point, the chipset sends a deferred reply for this transaction with
an implicit write-back response. For this erratum to occur, no snoop of this cache
line can be issued between the BIL and the deferred reply.
• The processor issues a write-combining store to the same cache line while data is
returning to the processor. This store straddles an 8-byte boundary.
• Due to an internal boundary condition, a time window exists where the L1 cache
contains corrupt data which could be accessed by a load.
Implication: No known commercially available chipsets trigger the failure conditions.
Workaround: The chipset could issue a BIL (snoop) to the deferred processor to eliminate the
failure conditions.
Status: For the steppings affected, see the Summary Tables of Changes.
49. Write Combining (WC) Load May Result in Unintended Address on
System Bus
Problem: When the processor performs a speculative write combining (WC) load, down the
path of a mispredicted branch, and the address happens to match a valid
UnCacheable (UC) address translation with the Data Translation Look-Aside Buffer,
an unintended UnCacheable load operation may be sent out on the system bus.
Implication: When this erratum occurs, an unintended load may be sent on system bus. Intel has
only encountered this erratum during pre-silicon simulation.
Workaround: It is possible for the BIOS to contain a workaround for this erratum.
Status: For the steppings affected, see the Summary Tables of Changes.
50. Incorrect Data May Be Returned When Page Tables Are in Write
Combining (WC) Memory Space
Problem: If page directories and/or page tables are located in Write Combining (WC) memory,
speculative loads to cacheable memory may complete with incorrect data.
Implication: Cacheable loads to memory mapped using page tables located in write combining
memory may return incorrect data. Intel has not been able to reproduce this erratum
with commercially available software.