Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
10 Design Guide
R
Figure 51. Example Speaker Circuit.......................................................................................107
Figure 52. Minimum IOAPIC Disable Topology......................................................................111
Figure 53. Example PIRQ Routing .........................................................................................111
Figure 54. SMBUS 2.0/SMLink Interface................................................................................113
Figure 55. Unified Vcc_Suspend Architecture........................................................................114
Figure 56. Unified Vcc_Core Architecture ..............................................................................114
Figure 57. Mixed Vcc_Suspend/Vcc_Core Architecture.........................................................115
Figure 58. FWH VPP Isolation Circuitry .................................................................................116
Figure 59. RTCX1 and SUSCLK Relationship in ICH3-M ......................................................117
Figure 60. External Circuitry for the ICH3-M RTC ..................................................................118
Figure 61. RTC Connections When Not Using Internal RTC .................................................118
Figure 62. A Diode Circuit to Connect RTC External Battery .................................................121
Figure 63. ICH3-M/LAN Connect Section (Dual Footprint Option) .........................................123
Figure 64. Single Solution Interconnect..................................................................................125
Figure 65. LAN_CLK Routing Example ..................................................................................126
Figure 66. Trace Routing........................................................................................................128
Figure 67. Ground Plane Separation ......................................................................................130
Figure 68. 82562EH Termination ...........................................................................................134
Figure 69. Critical Dimensions for Component Placement.....................................................135
Figure 70. 82562ET/82562EM Termination ...........................................................................137
Figure 71. Critical Dimensions for Component Placement.....................................................137
Figure 72. Termination Plane .................................................................................................139
Figure 73. Dual Footprint LAN Connect Interface ..................................................................140
Figure 74. Dual Footprint Analog Interface.............................................................................140
Figure 75. Processor BCLK Topology ....................................................................................144
Figure 76. ICH3-M Follows the CK-408 Power-up .................................................................145
Figure 77. PWRDWN# to CK-408..........................................................................................146
Figure 78. End of Line Termination Topology.........................................................................147
Figure 79. Source Shunt Termination Topology.....................................................................149
Figure 80. Clock Skew as Measured from Agent to Agent.....................................................151
Figure 81. Trace Spacing .......................................................................................................151
Figure 82. Topology for CLK66...............................................................................................152
Figure 83. Topology for AGPCLK to AGP Connector.............................................................153
Figure 84. Topology for AGPCLK to AGP Device Down ........................................................153
Figure 85. Topology for CLK33...............................................................................................154
Figure 86. Topology for CLK14...............................................................................................155
Figure 87. Topology for PCICLK to PCI Device Down ...........................................................156
Figure 88. Topology for PCICLK to PCI Slot ..........................................................................157
Figure 89. Topology for USB_CLOCK....................................................................................158
Figure 90. Platform Power Delivery Block Diagram ...............................................................160
Figure 91. Example 1.8-V/3.3-V Power Sequencing Circuit ...................................................163
Figure 92. Example 3.3-V/V5REF Sequencing Circuitry ........................................................164
Figure 93. V5REF_Sus Option 1: +V5_Always Available in Platform.....................................164
Figure 94. V5REF_Sus Option 1: +V5_Always Not Available in Platform ..............................165
Figure 95. DDR Power Delivery Block Diagram .....................................................................171
Figure 96. Intel 845MP/845MZ Chipset DDR Power Delivery Example .................................173
Figure 97. SMRCOMP Recommendation ..............................................................................180
Figure 98. Decoupling Capacitors Placement and Connectivity.............................................182