Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

104 Design Guide

• A 10-kΩ pull-down resistor to ground is on the PDIAG#/CBLID# signal is now required on the

Secondary Connector. This change is to prevent the GPI pin from floating if a device is not present

on the Secondary IDE interface.

9.2. PCI

The ICH3-M provides a PCI Bus interface that is compliant with the PCI Local Bus Specification

Revision 2.2

. The implementation is optimized for high-performance data streaming when the ICH3-M is

acting as either the target or the initiator on the PCI bus. For more information on the PCI Bus interface,

refer to the

PCI Local Bus Specification Revision 2.2.

The ICH3-M supports six PCI Bus masters (excluding the ICH3-M), by providing six REQ#/GNT#

pairs. In addition, the ICH3-M supports two PC/PCI REQ#/GNT# pairs, one of which is multiplexed

with a PCI REQ#/GNT# pair.

Figure 49. PCI Bus Layout Example

ICH3

9.3. AC’97

The ICH3-M implements an AC’97 2.1 compliant digital controller. Any Codec attached to the ICH3-M

AC-link must be AC’97 2.1 compliant as well. Please contact your Codec IHV for information on 2.1

compliant products. The AC’97 2.1 specification is on the Intel website:

http://developer.intel.com/ial/scalableplatforms/audio/index.htm

The AC-link is a bi-directional, serial PCM digital stream. It handles multiple input and output data

streams, as well as control register accesses, employing a time division multiplexed (TDM) scheme. The

AC-link architecture provides for data transfer through individual frames transmitted in a serial fashion.

Each frame is divided into 12 outgoing and 12 incoming data streams, or slots. The architecture of the

ICH3-M AC-link allows a maximum of two Codecs to be connected. The following figure shows a two-

Codec topology of the AC-link for the ICH3-M.