Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 105
R
Figure 50. ICH3-M AC’97 – Codec Connection
AC '97 2.1
controller
section of
the ICH3-M
Primary
Codec
SYNC
BIT_CLK
SDOUT
AC / MC / AMC
Digital
AC '97 2.1 Controller
RESET#
SDIN 0
Secondary
Codec
SDIN 1
AC / MC
9.3.1. Four-Layer Layout Example
Using the assumed 4-layer stack-up, the AC’97 interface can be routed using 5-mil traces with 5-mil
space between the traces. Maximum length between ICH3-M to CODEC/CNR is 14 inches in a “T”
topology. Trace impedance should be Z
0
= 55 Ω ± 15%.
Clocking is provided from the primary Codec on the link via BITCLK, and is derived from a 24.576-
MHz crystal or oscillator. Refer to the primary Codec vendor for crystal or oscillator requirements.
BITCLK is a 12.288-MHz clock driven by the primary Codec to the digital controller (ICH3-M), and
any other Codec present. That clock is used as the time base for latching and driving data.
The ICH3-M supports wake on ring from S1-S5 via the AC’97 link. The Codec asserts AC_SDINn to
wake the system. To provide wake capability and/or caller ID, standby power must be provided to the
modem Codec.
The ICH3-M has weak pull-downs/pull-ups that are only enabled when the AC-Link Shut Off bit in the
ICH3-M is set or if both function 5 and function 6 of device 31 are disabled (hidden). This will keep the
link from floating when the AC-link is off, or there are no Codecs present.
If the Shut-off bit is not set, or if neither function 5 nor function 6 of device 31 are disabled (hidden), it
implies that there is a Codec on the link. Therefore, BITCLK and AC_SDOUT will be driven by the
Codec and ICH3-M respectively. However, AC_SDIN0 and AC_SDIN1 may not be driven. If the link is
enabled, the assumption can be made that there is at least one codec.