Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

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Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 11

Tables

Table 1. Conventions and Terminology ................................................................................... 16

Table 2. Mobile Pentium 4 Processor-M in the 478-Pin Package Feature Set Overview........ 19

Table 3. Platform Bandwidth Summary.................................................................................... 23

Table 4. System Bus Routing Summary for the Processor...................................................... 26

Table 5. Processor System Bus Data Signal Routing Guidelines............................................ 30

Table 6. Processor System Bus Address Signal Routing Guidelines ...................................... 31

Table 7. Processor System Bus Control Signal Routing Guidelines........................................ 32

Table 8. Asynchronous AGTL+ Nets ....................................................................................... 34

Table 9. Layout Recommendations for Miscellaneous Signals – Topology 1.......................... 36

Table 10. Layout Recommendations for Miscellaneous Signals – Topology 2, 2A ................. 37

Table 11. Layout Recommendations for Miscellaneous Signals – Topology 2B ..................... 37

Table 12. Intel Mobile Pentium 4 Processor-M and Intel 845MP/845MZ Chipset Package

Lengths..................................................................................................................... 50

Table 13. Intel 845MP/845MZ DDR Signal Groups ................................................................. 54

Table 14. Data Signal Group Routing Guidelines .................................................................... 56

Table 15. DQ/CB to DQS Length Mismatch Mapping.............................................................. 57

Table 16. Control Signal SO-DIMM Mapping........................................................................... 62

Table 17. Control Signal Group Routing Guidelines

............................................................... 63

Table 18. Command Signal Group Routing Guidelines

.......................................................... 68

Table 19. Command Signal Group Routing Guidelines ........................................................... 73

Table 20. Clock Signal Mapping .............................................................................................. 77

Table 21. Clock Signal Group Routing Guidelines

................................................................. 78

Table 22. DDR Feedback Signal Routing Guidelines .............................................................. 82

Table 23. MCH-M DDR Signal Package Lengths .................................................................... 83

Table 24. AGP 2.0 Signal Groups............................................................................................ 86

Table 25. AGP 2.0 Data/Strobe Associations .......................................................................... 87

Table 26. Layout Routing Guidelines for AGP 1X Signals ....................................................... 88

Table 27. Layout Routing Guidelines for AGP 2X/4X Signals.................................................. 90

Table 28. AGP 2.0 Data Lengths Relative to Strobe Length.................................................... 90

Table 29. AGP 2.0 Routing Guideline Summary...................................................................... 91

Table 30. AGP 2.0 Pull-up Resistor Values ............................................................................. 93

Table 31. PLL0 Filter Routing Guidelines ................................................................................ 95

Table 32. PLL1 Routing Guidelines ......................................................................................... 96

Table 33. Recommended Inductor Components for MCH-M PLL Filter .................................. 96

Table 34. Recommended Capacitor Components for MCH-M PLL Filter................................ 96

Table 35. Hub Interface RCOMP Resistor Values................................................................... 97

Table 36. Hub Interface Signals............................................................................................... 98

Table 37. Hub Interface HUBREF Generation Circuit Specifications ...................................... 98

Table 38. IDE Signals ............................................................................................................ 100

Table 39. Codec Configurations............................................................................................. 106

Table 40. USB Signals ........................................................................................................... 110

Table 41. Integrated LAN Capability ...................................................................................... 123

Table 42. LAN Design Guide Section Reference................................................................... 124

Table 43. LAN Design Guide Point-to-Point Length Requirements ....................................... 125

Table 44. LAN Signals ........................................................................................................... 128

Table 45. 82562EH Home/PNA* Critical Dimensions for Component Placement................. 135

Table 46. 82562ET / 82562EM Critical Dimensions for Component Placement ................... 138

Table 47. Intel 845MP/845MZ Clock Groups ......................................................................... 142

Table 48. Platform System Clock Cross-reference................................................................ 143

Table 49. End of Line Termination Topology BCLK [1:0]# Routing Guidelines ..................... 148

Table 50. Source Shunt Termination Topology BCLK [1:0]# Routing Guidelines.................. 149

Table 51. CLK66 Routing Guidelines ..................................................................................... 152

Table 52. AGPCLK Routing Guidelines ................................................................................. 153