Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 111
R
To disable IOAPIC in BIOS:
• ICH3-M: D31:F0; Offset: D1; bit 0 (0=disable);
• Mobile Pentium 4 Processor-M: MSR 1Bh bit 11 (0 = disable)
Figure 52. Minimum IOAPIC Disable Topology
CK-408
ICH3-M
PCIF0 APICD0
APICD1
33Ω
ΩΩ
Ω
10KΩ
ΩΩ
Ω
APICLK
9.5.2. PIRQ Routing Example
PCI interrupt request signals E-H are new to the ICH3-M. These signals have been added to lower the
latency caused by having multiple devices on one Interrupt line. With these new signals, a system can be
designed to minimize sharing of PCI interrupt request lines.
Due to different system configurations, IRQ line routing to the PCI slots (“swizzling”) should be made to
minimize the sharing of interrupts between both internal ICH3-M functions and PCI functions. The
figure below shows an example of IRQ line routing to the PCI slots (note: it is not necessarily an optimal
routing scheme; an optimal scheme depends on individual system PCI IRQ usage).
Figure 53. Example PIRQ Routing
ICH3
PIRQA#
PIRQB#
PIRQC#
PIRQD#
PIRQE#
PIRQF#
PIRQG#
PIRQH#
INTA
INTB
INTC
INTD
INTA
INTB
INTC
INTD
INTA
INTB
INTC
INTD
INTA
INTB
INTC
INTD
Slot 1
PCI Device 0
(AD16 to IDSEL)
Slot 3
PCI Device 6
(AD22 to IDSEL)
Slot 4
PCI Device C
(AD28 to IDSEL)
Slot 2
PCI Device 5
(AD21 to IDSEL)
Example PIRQ Routing
ICH3-M