Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 113
R
Figure 54. SMBUS 2.0/SMLink Interface
ICH3-M
Host controller and
slave interface
SMBus
SMBCLK
SPD data
Temperature on
thermal sensor
Network
interface
card on PCI
Microcontroller
Intel(r)
Motherboard
LAN controller
Wire OR
SMLink0
SMLink1
SMLink
SMBDATA
smbus_smlink_IF
NOTE: Intel does not support external access of the ICH3-M’s Integrated LAN Controller via the SMLink interface.
Also, Intel does not support access of the ICH3-M’s SMBus Slave Interface by the ICH3-M’s SMBus Host
Controller.
9.6.1. SMBus Architecture and Design Considerations
9.6.1.1. SMBus Design Considerations
There are several possibilities for designing an SMBus using the ICH3-M. Designs can be grouped into
three major categories based on the power supply source for the SMBus microcontrollers. This includes
two unified designs, where either Vcc_Core or Vcc_Suspend powers all devices, and a mixed design
where some devices are powered by each of the two supplies.
Primary considerations in choosing a design are based on the following:
• Are there devices that must run in STR?
• Amount of Vcc_Suspend current available, i.e. minimizing load of Vcc_Suspend.
9.6.1.2. General Design Issues/Notes
Regardless of the architecture used, there are some general considerations.
The pull-up resistor size for the SMBus data and clock signals is dependent on the number of devices
present on the bus. A typical value is 8.2 KΩ. This should prevent the SMBus signals from floating,
which could cause leakage in the ICH3-M and other devices.
9.6.1.3. The Unified Vcc_ Suspend Architecture
In this design all SMBus devices are powered by the Vcc_Suspend supply. Consideration must be made
to provide enough Vcc_Suspend current while in STR.