Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
122 Design Guide
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Note that VBIAS is also very sensitive to environmental conditions.
9.9.7. SUSCLK
SUSCLK is a square waveform signal output from the RTC oscillation circuit. Depending on the quality
of the oscillation signal on RTCX1 (largest voltage swing), SUSCLK duty cycle can be between 30-70%.
If the SUSCLK duty cycle is beyond 30-70% range, it indicates a poor oscillation signal on RTCX1 and
RTCX2.
SUSCLK can be probed directly using normal probe (50-
Ω input impedance probe) and it is an
appropriated signal to check the RTC frequency to determine the accuracy of the ICH3-M’s RTC Clock
(see Application Note AP-728 for further details).
9.9.8. RTC-Well Input Strap Requirements
All RTC-well inputs (RSMRST#, RTCRST#, INTRUDER# and PWROK) must be either pulled up to
V
CC
RTC or pulled down to ground while in G3 state. RTCRST# when configured meets this
requirement. RSMRST# should have a weak external pull-down (8-22 KΩ) to ground and INTRUDER#
should have a weak external pull-up to V
CC
RTC. This will prevent these nodes from floating in G3, and
correspondingly will prevent I
CC
RTC leakage that can cause excessive coin-cell drain. The PWROK
input signal should also be configured with an external weak pull-down of 8-22 KΩ. The details are
shown in the figure below. The arrows in bold indicate the leakage paths if appropriate pull-ups and pull-
downs are not present.