Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel

Pentium

4 Processor-M and Intel

845MP/845MZ Chipset Platform

Design Guide 125

Figure 64. Single Solution Interconnect

ICH3

Platform

LAN

Connect

(PLC)

LAN_CLK

LAN_RSTSYNC

LAN_RXD[2:0]

LAN_TXD[2:0]

Table 43. LAN Design Guide Point-to-Point Length Requirements

Length Requirements From the Previous Figure

Configuration: A

82562EH L = 4.5” to 10” (Signal Lines LAN_RXD[2:1] and LAN_TXD[2:1] not connected)

82562ET L = 3.5” to 10”

CNR L = 3” to 9” (0.5” to 3” on card)

9.10.1.2. Signal Routing and Layout

LAN Connect signals must be carefully routed on the motherboard to meet the timing and signal quality

requirements of this interface specification. The following are some general guidelines that should be

followed. Intel recommends that the board designer simulate the board routing to verify that the

specifications are met for flight times and skews due to trace mismatch and crosstalk. On the

motherboard the length of each data trace is either equal in length to the LAN_CLK trace or up to 0.5

inches shorter than the LAN_CLK trace. (LAN_CLK should always be the longest motherboard trace in

each group.)

ICH3-M