Mobile Intel Pentium 4 Processor - M and Intel 845MP/MZ Chipset Platform Design Guide

Mobile Intel
®
Pentium
®
4 Processor-M and Intel
®
845MP/845MZ Chipset Platform
Design Guide 145
R
10.2. Clock Control
10.2.1. CK-408 Delay Circuit Recommendation
Ensure the processor gets power before receiving the clock. Follow Figure 76.
Figure 76. ICH3-M Follows the CK-408 Power-up
Delay Circuit
8-9ms
CK 408
VTT_PWRGD#
ICH3-M
V_GATE
VCC_CORE
10.2.2. SLP_S1#
When asserted SLP_S1# indicates that the system is in the S1-M power state. SLP_S1# needs to be
connected to clock generator PWRDWN# to shut off the system clocks in S1-M state. While entering S3
state, SLP_S1# initially asserts, but then goes high briefly when PCIRST# asserts, and then fades to
low/off when the ICH3-M main I/O power rail is switched off. The duration of SLP_S1# going high is
platform dependent since it is related to turning off of the ICH3-M main I/O power rail.
If SLP_S1# is directly connected to the PWRDWN# pin of a CK-408 compatible clock generator, then
during S3 entry, the clock generator's outputs may be momentarily turned ON when SLP_S1# deasserts
(due to PCIRST# assertion); and then turned OFF when the ICH3-MM main I/O power rail is switched
off (causing SLP_S1# to fade to low/off) or when power to the clock generator is turned off, whichever
occurs first. The clock restart and the subsequent clock stop are not guaranteed to be clean.
In systems that incorporate any peripherals which are not reset during S3 and which do not use
SUS_STAT# as an indicator of clock validity, ensure that the PWRDWN# pin of the CK-408-compatible
clock generator is not deasserted during S3 entry for a long enough duration such that the system clocks
can restart.
10.2.3. SLP_S3#
When asserted SLP_S3# indicates that the system is in the S3 power state.
If systems have problem with clocks being turned on during S1M to S3 transition, the designer can use
following recommendation. SLP_S3# pin be connected to clock generator PWRDWN# in combination
with the SLP_S1# signal to shut off the system clocks in S3 and during S1M to S3 transition.